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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Diff between revs 186 and 258

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Rev 186 Rev 258
Line 138... Line 138...
   //
   //
   // genpc_freeze_r
   // genpc_freeze_r
   //
   //
   always @(posedge clk or posedge rst)
   always @(posedge clk or posedge rst)
     if (rst)
     if (rst)
       genpc_refetch_r <= #1 1'b0;
       genpc_refetch_r <=  1'b0;
     else if (genpc_refetch)
     else if (genpc_refetch)
       genpc_refetch_r <= #1 1'b1;
       genpc_refetch_r <=  1'b1;
     else
     else
       genpc_refetch_r <= #1 1'b0;
       genpc_refetch_r <=  1'b0;
 
 
   //
   //
   // Async calculation of new PC value. This value is used for addressing the
   // Async calculation of new PC value. This value is used for addressing the
   // IC.
   // IC.
   //
   //
Line 256... Line 256...
   // PC register
   // PC register
   //
   //
   always @(posedge clk or posedge rst)
   always @(posedge clk or posedge rst)
     // default value 
     // default value 
     if (rst) begin
     if (rst) begin
        pcreg_default <= #1 `OR1200_BOOT_PCREG_DEFAULT; // jb
        pcreg_default <=  `OR1200_BOOT_PCREG_DEFAULT; // jb
        pcreg_select <= #1 1'b1;// select async. value due to reset state
        pcreg_select <=  1'b1;// select async. value due to reset state
     end
     end
   // selected value (different from default) is written into FF after
   // selected value (different from default) is written into FF after
   // reset state
   // reset state
     else if (pcreg_select) begin
     else if (pcreg_select) begin
        // dynamic value can only be assigned to FF out of reset! 
        // dynamic value can only be assigned to FF out of reset! 
        pcreg_default <= #1 pcreg_boot[31:2];
        pcreg_default <=  pcreg_boot[31:2];
        pcreg_select <= #1 1'b0;                // select FF value 
        pcreg_select <=  1'b0;          // select FF value 
     end
     end
     else if (spr_pc_we) begin
     else if (spr_pc_we) begin
        pcreg_default <= #1 spr_dat_i[31:2];
        pcreg_default <=  spr_dat_i[31:2];
     end
     end
     else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i
     else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i
              & !genpc_refetch) begin
              & !genpc_refetch) begin
        pcreg_default <= #1 pc[31:2];
        pcreg_default <=  pc[31:2];
     end
     end
 
 
   // select async. value for pcreg after reset - PC jumps to the address selected
   // select async. value for pcreg after reset - PC jumps to the address selected
   // after boot.
   // after boot.
   assign  pcreg_boot = `OR1200_BOOT_ADR; // changed JB
   assign  pcreg_boot = `OR1200_BOOT_ADR; // changed JB

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