URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_gmultp2_32x32.v] - Diff between revs 10 and 141

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Rev 10	Rev 141
Line 41...	Line 41...
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: or1200_gmultp2_32x32.v,v $`
	`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
	`// No update`
	`//`
	`// Revision 1.2 2002/07/31 02:04:35 lampret`
	`// MAC now follows software convention (signed multiply instead of unsigned).`
	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`	`//`
`// Revision 1.4 2001/12/04 05:02:35 lampret`	`// Revision 1.4 2001/12/04 05:02:35 lampret`
`// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32`	`// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32`
Line 95...	Line 101...
`integer yi;`	`integer yi;`

`//`	`//`
`// Conversion unsigned to signed`	`// Conversion unsigned to signed`
`//`	`//`
	`/* verilator lint_off COMBDLY */`
`always @(X)`	`always @(X)`
`xi <= X;`	`xi <= X;`

`//`	`//`
`// Conversion unsigned to signed`	`// Conversion unsigned to signed`
`//`	`//`
`always @(Y)`	`always @(Y)`
`yi <= Y;`	`yi <= Y;`
	`/* verilator lint_on COMBDLY */`
`//`	`//`
`// First multiply stage`	`// First multiply stage`
`//`	`//`
`always @(posedge CLK or posedge RST)`	`always @(posedge CLK or posedge RST)`
`if (RST)`	`if (RST)`

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_gmultp2_32x32.v] - Diff between revs 10 and 141