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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_gmultp2_32x32.v] - Diff between revs 141 and 258
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Rev 141 |
Rev 258 |
Line 118... |
Line 118... |
//
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//
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always @(posedge CLK or posedge RST)
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always @(posedge CLK or posedge RST)
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if (RST)
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if (RST)
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p0 <= `OR1200_WW'b0;
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p0 <= `OR1200_WW'b0;
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else
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else
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p0 <= #1 xi * yi;
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p0 <= xi * yi;
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//
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//
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// Second multiply stage
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// Second multiply stage
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//
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//
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always @(posedge CLK or posedge RST)
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always @(posedge CLK or posedge RST)
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if (RST)
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if (RST)
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p1 <= `OR1200_WW'b0;
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p1 <= `OR1200_WW'b0;
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else
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else
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p1 <= #1 p0;
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p1 <= p0;
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assign P = p1;
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assign P = p1;
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endmodule
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endmodule
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