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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_gmultp2_32x32.v] - Diff between revs 141 and 258

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Rev 141 Rev 258
Line 118... Line 118...
//
//
always @(posedge CLK or posedge RST)
always @(posedge CLK or posedge RST)
        if (RST)
        if (RST)
                p0 <= `OR1200_WW'b0;
                p0 <= `OR1200_WW'b0;
        else
        else
                p0 <= #1 xi * yi;
                p0 <=  xi * yi;
 
 
//
//
// Second multiply stage
// Second multiply stage
//
//
always @(posedge CLK or posedge RST)
always @(posedge CLK or posedge RST)
        if (RST)
        if (RST)
                p1 <= `OR1200_WW'b0;
                p1 <= `OR1200_WW'b0;
        else
        else
                p1 <= #1 p0;
                p1 <=  p0;
 
 
assign P = p1;
assign P = p1;
 
 
endmodule
endmodule
 
 

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