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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 358 |
Line 134... |
Line 134... |
!cache_inhibit | (state == `OR1200_ICFSM_LREFILL3);
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!cache_inhibit | (state == `OR1200_ICFSM_LREFILL3);
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//
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//
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// Main IC FSM
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// Main IC FSM
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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state <= `OR1200_ICFSM_IDLE;
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state <= `OR1200_ICFSM_IDLE;
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saved_addr_r <= 32'b0;
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saved_addr_r <= 32'b0;
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hitmiss_eval <= 1'b0;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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load <= 1'b0;
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cnt <= 3'b000;
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cnt <= 3'b000;
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