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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_fsm.v] - Diff between revs 358 and 481

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Rev 358 Rev 481
Line 56... Line 56...
`define OR1200_ICFSM_CFETCH     2'd1
`define OR1200_ICFSM_CFETCH     2'd1
`define OR1200_ICFSM_LREFILL3   2'd2
`define OR1200_ICFSM_LREFILL3   2'd2
`define OR1200_ICFSM_IFETCH     2'd3
`define OR1200_ICFSM_IFETCH     2'd3
 
 
//
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
// Instruction cache FSM
//
//
 
 
module or1200_ic_fsm(
module or1200_ic_fsm(
        // Clock and reset
        // Clock and reset
        clk, rst,
        clk, rst,
 
 
        // Internal i/f to top level IC
        // Internal i/f to top level IC
        ic_en, icqmem_cycstb_i, icqmem_ci_i,
        ic_en, icqmem_cycstb_i, icqmem_ci_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        tagcomp_miss,
        icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
        biudata_valid, biudata_error,
        burst, tag_we
        start_addr, saved_addr,
 
        icram_we, tag_we,
 
        biu_read,
 
        first_hit_ack, first_miss_ack, first_miss_err,
 
        burst
);
);
 
 
//
//
// I/O
// I/O
//
//
Line 96... Line 100...
//
//
// Internal wires and regs
// Internal wires and regs
//
//
reg     [31:0]                   saved_addr_r;
reg     [31:0]                   saved_addr_r;
reg     [1:0]                    state;
reg     [1:0]                    state;
reg     [2:0]                    cnt;
reg [`OR1200_ICLS-1:0]           cnt;
reg                             hitmiss_eval;
reg                             hitmiss_eval;
reg                             load;
reg                             load;
reg                             cache_inhibit;
reg                             cache_inhibit;
 
reg                             last_eval_miss; // JPB
 
 
   //
   //
   // Generate of ICRAM write enables
   // Generate of ICRAM write enables
   //
   //
   assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
   assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
Line 140... Line 145...
      if (rst == `OR1200_RST_VALUE) begin
      if (rst == `OR1200_RST_VALUE) begin
         state <=  `OR1200_ICFSM_IDLE;
         state <=  `OR1200_ICFSM_IDLE;
         saved_addr_r <=  32'b0;
         saved_addr_r <=  32'b0;
         hitmiss_eval <=  1'b0;
         hitmiss_eval <=  1'b0;
         load <=  1'b0;
         load <=  1'b0;
         cnt <=  3'b000;
         cnt <=  `OR1200_ICLS'd0;
         cache_inhibit <=  1'b0;
         cache_inhibit <=  1'b0;
 
         last_eval_miss <= 0; // JPB
 
 
      end
      end
      else
      else
        case (state)    // synopsys parallel_case
        case (state)    // synopsys parallel_case
          `OR1200_ICFSM_IDLE :
          `OR1200_ICFSM_IDLE :
            if (ic_en & icqmem_cycstb_i) begin          // fetch
            if (ic_en & icqmem_cycstb_i) begin          // fetch
               state <=  `OR1200_ICFSM_CFETCH;
               state <=  `OR1200_ICFSM_CFETCH;
               saved_addr_r <=  start_addr;
               saved_addr_r <=  start_addr;
               hitmiss_eval <=  1'b1;
               hitmiss_eval <=  1'b1;
               load <=  1'b1;
               load <=  1'b1;
               cache_inhibit <=  icqmem_ci_i;
               cache_inhibit <=  icqmem_ci_i;
 
               last_eval_miss <= 0; // JPB
            end
            end
            else begin                  // idle
            else begin                  // idle
               hitmiss_eval <=  1'b0;
               hitmiss_eval <=  1'b0;
               load <=  1'b0;
               load <=  1'b0;
               cache_inhibit <=  1'b0;
               cache_inhibit <=  1'b0;
Line 164... Line 172...
 
 
             if (icqmem_cycstb_i & icqmem_ci_i)
             if (icqmem_cycstb_i & icqmem_ci_i)
               cache_inhibit <=  1'b1;
               cache_inhibit <=  1'b1;
 
 
             if (hitmiss_eval)
             if (hitmiss_eval)
               saved_addr_r[31:13] <=  start_addr[31:13];
               saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];
 
 
             if ((!ic_en) ||
             if ((!ic_en) ||
                 // fetch aborted (usually caused by IMMU)
                 // fetch aborted (usually caused by IMMU)
                 (hitmiss_eval & !icqmem_cycstb_i) ||
                 (hitmiss_eval & !icqmem_cycstb_i) ||
                 (biudata_error) ||  // fetch terminated with an error
                 (biudata_error) ||  // fetch terminated with an error
                 // fetch from cache-inhibited page
                 // fetch from cache-inhibited page
Line 177... Line 184...
                state <=  `OR1200_ICFSM_IDLE;
                state <=  `OR1200_ICFSM_IDLE;
                hitmiss_eval <=  1'b0;
                hitmiss_eval <=  1'b0;
                load <=  1'b0;
                load <=  1'b0;
                cache_inhibit <=  1'b0;
                cache_inhibit <=  1'b0;
             end // if ((!ic_en) ||...       
             end // if ((!ic_en) ||...       
             // fetch missed, finish current external fetch and refill
             // fetch missed, wait for first fetch and continue filling line
             else if (tagcomp_miss & biudata_valid) begin
             else if (tagcomp_miss & biudata_valid) begin
                state <=  `OR1200_ICFSM_LREFILL3;
                state <=  `OR1200_ICFSM_LREFILL3;
                saved_addr_r[3:2] <=  saved_addr_r[3:2] + 1'd1;
                saved_addr_r[`OR1200_ICLS-1:2]
 
                  <= saved_addr_r[`OR1200_ICLS-1:2] + 1;
                hitmiss_eval <=  1'b0;
                hitmiss_eval <=  1'b0;
                cnt <=  `OR1200_ICLS-2;
                cnt <= ((1 << `OR1200_ICLS) - (2 * 4));
                cache_inhibit <=  1'b0;
                cache_inhibit <=  1'b0;
             end
             end
             // fetch aborted (usually caused by exception)
             // fetch aborted (usually caused by exception)
             else if (!icqmem_cycstb_i) begin
             else if (!icqmem_cycstb_i
 
                      & !last_eval_miss // JPB
 
                      ) begin
                state <=  `OR1200_ICFSM_IDLE;
                state <=  `OR1200_ICFSM_IDLE;
                hitmiss_eval <=  1'b0;
                hitmiss_eval <=  1'b0;
                load <=  1'b0;
                load <=  1'b0;
                cache_inhibit <=  1'b0;
                cache_inhibit <=  1'b0;
             end
             end
             // fetch hit, finish immediately
             // fetch hit, wait in this state for now
             else if (!tagcomp_miss & !icqmem_ci_i) begin
             else if (!tagcomp_miss & !icqmem_ci_i) begin
                saved_addr_r <=  start_addr;
                saved_addr_r <=  start_addr;
                cache_inhibit <=  1'b0;
                cache_inhibit <=  1'b0;
             end
             end
             else   // fetch in-progress
             else   // fetch in-progress
               hitmiss_eval <=  1'b0;
               hitmiss_eval <=  1'b0;
 
 
 
             if (hitmiss_eval & !tagcomp_miss) // JPB
 
               last_eval_miss <= 1; // JPB
 
 
          end
          end
          `OR1200_ICFSM_LREFILL3 : begin
          `OR1200_ICFSM_LREFILL3 : begin
             // abort because IC has just been turned off
             // abort because IC has just been turned off
             if (!ic_en) begin
             if (!ic_en) begin
                // invalidate before IC can be turned on
                // invalidate before IC can be turned on
Line 211... Line 225...
                hitmiss_eval <=  1'b0;
                hitmiss_eval <=  1'b0;
                load <=  1'b0;
                load <=  1'b0;
             end
             end
             // refill ack, more fetchs to come
             // refill ack, more fetchs to come
             else if (biudata_valid && (|cnt)) begin
             else if (biudata_valid && (|cnt)) begin
                cnt <=  cnt - 3'd1;
                cnt <=  cnt - `OR1200_ICLS'd4;
                saved_addr_r[3:2] <=  saved_addr_r[3:2] + 1'd1;
                saved_addr_r[`OR1200_ICLS-1:2]
 
                  <= saved_addr_r[`OR1200_ICLS-1:2] + 1;
             end
             end
             // last fetch of line refill
             // last fetch of line refill
             else if (biudata_valid) begin
             else if (biudata_valid) begin
                state <=  `OR1200_ICFSM_IDLE;
                state <=  `OR1200_ICFSM_IDLE;
                saved_addr_r <=  start_addr;
                saved_addr_r <=  start_addr;

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