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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_ic_fsm.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Bugs fixed.
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//
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// Revision 1.10 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.9 2004/04/05 08:29:57 lampret
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// Revision 1.9 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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// Merged branch_qmem into main tree.
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//
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//
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// Revision 1.8.4.1 2003/07/08 15:36:37 lampret
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// Revision 1.8.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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// Added embedded memory QMEM.
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Line 178... |
//
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//
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// Assert for cache hit first word ready
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// Assert for cache hit first word ready
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded with an error
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// Assert for cache miss first word stored/loaded with an error
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//
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//
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assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icqmem_ci_i;
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assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit;
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assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
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assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
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assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
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assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
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//
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//
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// Assert burst when doing reload of complete cache line
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// Assert burst when doing reload of complete cache line
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Line 208... |
if (ic_en & icqmem_cycstb_i) begin // fetch
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if (ic_en & icqmem_cycstb_i) begin // fetch
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state <= #1 `OR1200_ICFSM_CFETCH;
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state <= #1 `OR1200_ICFSM_CFETCH;
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saved_addr_r <= #1 start_addr;
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saved_addr_r <= #1 start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= #1 1'b1;
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load <= #1 1'b1;
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load <= #1 1'b1;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 icqmem_ci_i;
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end
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end
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else begin // idle
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else begin // idle
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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Line 236... |
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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cnt <= #1 `OR1200_ICLS-2;
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cnt <= #1 `OR1200_ICLS-2;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
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saved_addr_r <= #1 start_addr;
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cache_inhibit <= #1 1'b0;
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end
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else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
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else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
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saved_addr_r <= #1 start_addr;
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cache_inhibit <= #1 1'b0;
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end
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else // fetch in-progress
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else // fetch in-progress
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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end
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end
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`OR1200_ICFSM_LREFILL3 : begin
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`OR1200_ICFSM_LREFILL3 : begin
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if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
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if (!ic_en) begin // abort because IC has just been turned off
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state <= #1 `OR1200_ICFSM_IDLE; // invalidate before IC can be turned on
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saved_addr_r <= #1 start_addr;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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end
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else if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
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cnt <= #1 cnt - 3'd1;
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cnt <= #1 cnt - 3'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
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end
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end
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else if (biudata_valid) begin // last fetch of line refill
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else if (biudata_valid) begin // last fetch of line refill
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= #1 `OR1200_ICFSM_IDLE;
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