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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's IC FSM ////
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//// OR1200's IC FSM ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Insn cache state machine ////
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//// Insn cache state machine ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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// $Log: or1200_ic_fsm.v,v $
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// $Log: or1200_ic_fsm.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Bugs fixed.
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// Bugs fixed.
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//
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//
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// Revision 1.10 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.9 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.8.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.8 2003/06/06 02:54:47 lampret
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// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
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//
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// Revision 1.7 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.6 2002/03/28 19:10:40 lampret
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// Optimized cache controller FSM.
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//
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// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
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// First import of the "new" XESS XSV environment.
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//
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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//
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//
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// Assert for cache hit first word ready
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// Assert for cache hit first word ready
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded OK
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// Assert for cache miss first word stored/loaded with an error
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// Assert for cache miss first word stored/loaded with an error
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//
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//
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assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit;
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assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval &
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!tagcomp_miss & !cache_inhibit;
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assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
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assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
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assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
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assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
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//
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//
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// Assert burst when doing reload of complete cache line
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// Assert burst when doing reload of complete cache line
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//
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//
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assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
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assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss &
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| (state == `OR1200_ICFSM_LREFILL3);
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!cache_inhibit | (state == `OR1200_ICFSM_LREFILL3);
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//
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//
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// Main IC FSM
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// Main IC FSM
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= `OR1200_ICFSM_IDLE;
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saved_addr_r <= #1 32'b0;
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saved_addr_r <= 32'b0;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= 1'b0;
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load <= #1 1'b0;
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load <= 1'b0;
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cnt <= #1 3'b000;
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cnt <= 3'b000;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= 1'b0;
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end
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end
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else
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else
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case (state) // synopsys parallel_case
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case (state) // synopsys parallel_case
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`OR1200_ICFSM_IDLE :
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`OR1200_ICFSM_IDLE :
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if (ic_en & icqmem_cycstb_i) begin // fetch
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if (ic_en & icqmem_cycstb_i) begin // fetch
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state <= #1 `OR1200_ICFSM_CFETCH;
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state <= `OR1200_ICFSM_CFETCH;
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saved_addr_r <= #1 start_addr;
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saved_addr_r <= start_addr;
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hitmiss_eval <= #1 1'b1;
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hitmiss_eval <= 1'b1;
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load <= #1 1'b1;
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load <= 1'b1;
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cache_inhibit <= #1 icqmem_ci_i;
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cache_inhibit <= icqmem_ci_i;
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end
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end
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else begin // idle
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else begin // idle
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= 1'b0;
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load <= #1 1'b0;
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load <= 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= 1'b0;
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end
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end
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`OR1200_ICFSM_CFETCH: begin // fetch
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`OR1200_ICFSM_CFETCH: begin // fetch
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if (icqmem_cycstb_i & icqmem_ci_i)
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if (icqmem_cycstb_i & icqmem_ci_i)
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cache_inhibit <= #1 1'b1;
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cache_inhibit <= 1'b1;
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if (hitmiss_eval)
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if (hitmiss_eval)
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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saved_addr_r[31:13] <= start_addr[31:13];
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if ((!ic_en) ||
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if ((!ic_en) ||
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(hitmiss_eval & !icqmem_cycstb_i) || // fetch aborted (usually caused by IMMU)
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// fetch aborted (usually caused by IMMU)
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(hitmiss_eval & !icqmem_cycstb_i) ||
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(biudata_error) || // fetch terminated with an error
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(biudata_error) || // fetch terminated with an error
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(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
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// fetch from cache-inhibited page
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state <= #1 `OR1200_ICFSM_IDLE;
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(cache_inhibit & biudata_valid)) begin
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hitmiss_eval <= #1 1'b0;
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state <= `OR1200_ICFSM_IDLE;
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load <= #1 1'b0;
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hitmiss_eval <= 1'b0;
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cache_inhibit <= #1 1'b0;
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load <= 1'b0;
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end
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cache_inhibit <= 1'b0;
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else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
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end // if ((!ic_en) ||...
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state <= #1 `OR1200_ICFSM_LREFILL3;
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// fetch missed, finish current external fetch and refill
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
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else if (tagcomp_miss & biudata_valid) begin
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hitmiss_eval <= #1 1'b0;
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state <= `OR1200_ICFSM_LREFILL3;
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cnt <= #1 `OR1200_ICLS-2;
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saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
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cache_inhibit <= #1 1'b0;
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hitmiss_eval <= 1'b0;
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end
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cnt <= `OR1200_ICLS-2;
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else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
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cache_inhibit <= 1'b0;
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state <= #1 `OR1200_ICFSM_IDLE;
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end
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hitmiss_eval <= #1 1'b0;
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// fetch aborted (usually caused by exception)
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load <= #1 1'b0;
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else if (!icqmem_cycstb_i) begin
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cache_inhibit <= #1 1'b0;
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state <= `OR1200_ICFSM_IDLE;
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end
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hitmiss_eval <= 1'b0;
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else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
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load <= 1'b0;
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saved_addr_r <= #1 start_addr;
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cache_inhibit <= 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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// fetch hit, finish immediately
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else if (!tagcomp_miss & !icqmem_ci_i) begin
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saved_addr_r <= start_addr;
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cache_inhibit <= 1'b0;
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end
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end
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else // fetch in-progress
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else // fetch in-progress
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= 1'b0;
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end
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end
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`OR1200_ICFSM_LREFILL3 : begin
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`OR1200_ICFSM_LREFILL3 : begin
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if (!ic_en) begin // abort because IC has just been turned off
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// abort because IC has just been turned off
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state <= #1 `OR1200_ICFSM_IDLE; // invalidate before IC can be turned on
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if (!ic_en) begin
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saved_addr_r <= #1 start_addr;
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// invalidate before IC can be turned on
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hitmiss_eval <= #1 1'b0;
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state <= `OR1200_ICFSM_IDLE;
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load <= #1 1'b0;
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saved_addr_r <= start_addr;
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end
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hitmiss_eval <= 1'b0;
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else if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
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load <= 1'b0;
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cnt <= #1 cnt - 3'd1;
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end
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
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// refill ack, more fetchs to come
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end
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else if (biudata_valid && (|cnt)) begin
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else if (biudata_valid) begin // last fetch of line refill
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cnt <= cnt - 3'd1;
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state <= #1 `OR1200_ICFSM_IDLE;
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saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
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saved_addr_r <= #1 start_addr;
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end
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hitmiss_eval <= #1 1'b0;
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// last fetch of line refill
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load <= #1 1'b0;
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else if (biudata_valid) begin
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state <= `OR1200_ICFSM_IDLE;
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saved_addr_r <= start_addr;
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hitmiss_eval <= 1'b0;
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load <= 1'b0;
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end
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end
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end
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end
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default:
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default:
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state <= #1 `OR1200_ICFSM_IDLE;
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state <= `OR1200_ICFSM_IDLE;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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