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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Diff between revs 141 and 481

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Rev 141 Rev 481
Line 46... Line 46...
// $Log: or1200_ic_ram.v,v $
// $Log: or1200_ic_ram.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Minor update: 
// Coding style changed.
// Coding style changed.
//
//
// Revision 1.6  2004/06/08 18:17:36  lampret
 
// Non-functional changes. Coding style fixes.
 
//
 
// Revision 1.5  2004/04/08 11:00:46  simont
 
// Add support for 512B instruction cache.
 
//
 
// Revision 1.4  2004/04/05 08:29:57  lampret
 
// Merged branch_qmem into main tree.
 
//
 
// Revision 1.2.4.1  2003/12/09 11:46:48  simons
 
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
 
//
 
// Revision 1.2  2002/10/17 20:04:40  lampret
 
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
 
//
 
// Revision 1.1  2002/01/03 08:16:15  lampret
 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
 
//
 
// Revision 1.9  2001/10/21 17:57:16  lampret
 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
 
//
 
// Revision 1.8  2001/10/14 13:12:09  lampret
 
// MP3 version.
 
//
 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
 
// no message
 
//
 
// Revision 1.3  2001/08/09 13:39:33  lampret
 
// Major clean-up.
 
//
 
// Revision 1.2  2001/07/22 03:31:54  lampret
 
// Fixed RAM's oen bug. Cache bypass under development.
 
//
 
// Revision 1.1  2001/07/20 00:46:03  lampret
 
// Development version of RTL. Libraries are missing.
 
//
 
//
 
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"
Line 140... Line 103...
`else
`else
 
 
//
//
// Instantiation of IC RAM block
// Instantiation of IC RAM block
//
//
`ifdef OR1200_IC_1W_512B
 
   or1200_spram #
 
     (
 
      .aw(9),
 
      .dw(32)
 
      )
 
`endif
 
`ifdef OR1200_IC_1W_4KB
 
   or1200_spram #
   or1200_spram #
     (
     (
      .aw(10),
      .aw(`OR1200_ICINDX),
      .dw(32)
      .dw(32)
      )
      )
`endif
 
`ifdef OR1200_IC_1W_8KB
 
   or1200_spram #
 
     (
 
      .aw(11),
 
      .dw(32)
 
      )
 
`endif
 
   ic_ram0
   ic_ram0
     (
     (
`ifdef OR1200_BIST
`ifdef OR1200_BIST
      // RAM BIST
      // RAM BIST
      .mbist_si_i(mbist_si_i),
      .mbist_si_i(mbist_si_i),

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