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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 141 |
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_ic_ram.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Coding style changed.
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//
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// Revision 1.6 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.5 2004/04/08 11:00:46 simont
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// Revision 1.5 2004/04/08 11:00:46 simont
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// Add support for 512B instruction cache.
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// Add support for 512B instruction cache.
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//
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//
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// Revision 1.4 2004/04/05 08:29:57 lampret
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// Revision 1.4 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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// Merged branch_qmem into main tree.
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Line 141... |
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//
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//
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// Instantiation of IC RAM block
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// Instantiation of IC RAM block
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//
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//
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`ifdef OR1200_IC_1W_512B
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`ifdef OR1200_IC_1W_512B
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or1200_spram_128x32 ic_ram0(
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or1200_spram #
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(
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.aw(9),
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.dw(32)
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)
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`endif
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`endif
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`ifdef OR1200_IC_1W_4KB
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`ifdef OR1200_IC_1W_4KB
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or1200_spram_1024x32 ic_ram0(
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or1200_spram #
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(
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.aw(10),
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.dw(32)
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)
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`endif
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`endif
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`ifdef OR1200_IC_1W_8KB
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`ifdef OR1200_IC_1W_8KB
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or1200_spram_2048x32 ic_ram0(
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or1200_spram #
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(
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.aw(11),
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.dw(32)
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)
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`endif
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`endif
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ic_ram0
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(
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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.mbist_si_i(mbist_si_i),
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.mbist_si_i(mbist_si_i),
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.mbist_so_o(mbist_so_o),
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.mbist_so_o(mbist_so_o),
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.mbist_ctrl_i(mbist_ctrl_i),
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.mbist_ctrl_i(mbist_ctrl_i),
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`endif
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`endif
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.ce(en),
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.ce(en),
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.we(we[0]),
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.we(we[0]),
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.oe(1'b1),
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//.oe(1'b1),
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.addr(addr),
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.addr(addr),
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.di(datain),
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.di(datain),
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.doq(dataout)
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.doq(dataout)
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);
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);
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`endif
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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