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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Diff between revs 10 and 141

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////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_ic_ram.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Coding style changed.
 
//
 
// Revision 1.6  2004/06/08 18:17:36  lampret
 
// Non-functional changes. Coding style fixes.
 
//
// Revision 1.5  2004/04/08 11:00:46  simont
// Revision 1.5  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
// Add support for 512B instruction cache.
//
//
// Revision 1.4  2004/04/05 08:29:57  lampret
// Revision 1.4  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
// Merged branch_qmem into main tree.
Line 134... Line 141...
 
 
//
//
// Instantiation of IC RAM block
// Instantiation of IC RAM block
//
//
`ifdef OR1200_IC_1W_512B
`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
   or1200_spram #
 
     (
 
      .aw(9),
 
      .dw(32)
 
      )
`endif
`endif
`ifdef OR1200_IC_1W_4KB
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
   or1200_spram #
 
     (
 
      .aw(10),
 
      .dw(32)
 
      )
`endif
`endif
`ifdef OR1200_IC_1W_8KB
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
   or1200_spram #
 
     (
 
      .aw(11),
 
      .dw(32)
 
      )
`endif
`endif
 
   ic_ram0
 
     (
`ifdef OR1200_BIST
`ifdef OR1200_BIST
        // RAM BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
`endif
        .clk(clk),
        .clk(clk),
        .rst(rst),
 
        .ce(en),
        .ce(en),
        .we(we[0]),
        .we(we[0]),
        .oe(1'b1),
      //.oe(1'b1),
        .addr(addr),
        .addr(addr),
        .di(datain),
        .di(datain),
        .doq(dataout)
        .doq(dataout)
);
);
 
 
`endif
`endif
 
 
endmodule
endmodule
 
 
 
 
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