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Line 46... |
// $Log: or1200_ic_ram.v,v $
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// $Log: or1200_ic_ram.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Coding style changed.
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// Coding style changed.
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//
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//
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// Revision 1.6 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.5 2004/04/08 11:00:46 simont
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// Add support for 512B instruction cache.
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//
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// Revision 1.4 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.2.4.1 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.2 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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Line 103... |
`else
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`else
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//
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//
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// Instantiation of IC RAM block
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// Instantiation of IC RAM block
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//
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//
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`ifdef OR1200_IC_1W_512B
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or1200_spram #
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(
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.aw(9),
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.dw(32)
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)
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`endif
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`ifdef OR1200_IC_1W_4KB
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or1200_spram #
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or1200_spram #
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(
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(
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.aw(10),
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.aw(`OR1200_ICINDX),
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.dw(32)
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.dw(32)
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)
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)
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`endif
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`ifdef OR1200_IC_1W_8KB
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or1200_spram #
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(
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.aw(11),
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.dw(32)
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)
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`endif
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ic_ram0
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ic_ram0
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(
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(
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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.mbist_si_i(mbist_si_i),
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.mbist_si_i(mbist_si_i),
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