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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_if.v] - Diff between revs 141 and 258

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  OR1200's instruction fetch                                  ////
////  OR1200's instruction fetch                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  PC, instruction fetch, interface to IC.                     ////
////  PC, instruction fetch, interface to IC.                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
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//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
 
//
 
// $Log: or1200_if.v,v $
// $Log: or1200_if.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Major update: 
// Structure reordered and bugs fixed. 
// Structure reordered and bugs fixed. 
//
 
// Revision 1.5  2004/04/05 08:29:57  lampret
 
// Merged branch_qmem into main tree.
 
//
 
// Revision 1.3  2002/03/29 15:16:56  lampret
 
// Some of the warnings fixed.
 
//
 
// Revision 1.2  2002/01/28 01:16:00  lampret
 
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
 
//
 
// Revision 1.1  2002/01/03 08:16:15  lampret
 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
 
//
 
// Revision 1.10  2001/11/20 18:46:15  simons
 
// Break point bug fixed
 
//
 
// Revision 1.9  2001/11/18 09:58:28  lampret
 
// Fixed some l.trap typos.
 
//
 
// Revision 1.8  2001/11/18 08:36:28  lampret
 
// For GDB changed single stepping and disabled trap exception.
 
//
 
// Revision 1.7  2001/10/21 17:57:16  lampret
 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
 
//
 
// Revision 1.6  2001/10/14 13:12:09  lampret
 
// MP3 version.
 
//
 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
 
// no message
 
//
 
// Revision 1.1  2001/08/09 13:39:33  lampret
 
// Major clean-up.
 
//
 
//
 
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"
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//
//
assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
 
 
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                if_bypass_reg <= #1 1'b0;
                if_bypass_reg <=  1'b0;
        else
        else
                if_bypass_reg <= #1 if_bypass;
                if_bypass_reg <=  if_bypass;
 
 
//
//
// IF stage insn
// IF stage insn
//
//
assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
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//
//
// Flag for saved insn/address
// Flag for saved insn/address
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                saved <= #1 1'b0;
                saved <=  1'b0;
        else if (if_flushpipe)
        else if (if_flushpipe)
                saved <= #1 1'b0;
                saved <=  1'b0;
        else if (save_insn)
        else if (save_insn)
                saved <= #1 1'b1;
                saved <=  1'b1;
        else if (!if_freeze)
        else if (!if_freeze)
                saved <= #1 1'b0;
                saved <=  1'b0;
 
 
//
//
// Store fetched instruction
// Store fetched instruction
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (if_flushpipe)
        else if (if_flushpipe)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (save_insn)
        else if (save_insn)
                insn_saved <= #1 icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
                insn_saved <=  icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
        else if (!if_freeze)
        else if (!if_freeze)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
 
 
//
//
// Store fetched instruction's address
// Store fetched instruction's address
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                addr_saved <= #1 32'h00000000;
                addr_saved <=  32'h00000000;
        else if (if_flushpipe)
        else if (if_flushpipe)
                addr_saved <= #1 32'h00000000;
                addr_saved <=  32'h00000000;
        else if (save_insn)
        else if (save_insn)
                addr_saved <= #1 {icpu_adr_i[31:2], 2'b00};
                addr_saved <=  {icpu_adr_i[31:2], 2'b00};
        else if (!if_freeze)
        else if (!if_freeze)
                addr_saved <= #1 {icpu_adr_i[31:2], 2'b00};
                addr_saved <=  {icpu_adr_i[31:2], 2'b00};
 
 
//
//
// Store fetched instruction's error tags 
// Store fetched instruction's error tags 
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                err_saved <= #1 3'b000;
                err_saved <=  3'b000;
        else if (if_flushpipe)
        else if (if_flushpipe)
                err_saved <= #1 3'b000;
                err_saved <=  3'b000;
        else if (save_insn) begin
        else if (save_insn) begin
                err_saved[0] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
                err_saved[0] <=  icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
                err_saved[1] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
                err_saved[1] <=  icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
                err_saved[2] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
                err_saved[2] <=  icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
        end
        end
        else if (!if_freeze)
        else if (!if_freeze)
                err_saved <= #1 3'b000;
                err_saved <=  3'b000;
 
 
 
 
endmodule
endmodule
 
 
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