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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_if.v] - Diff between revs 258 and 358

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Rev 258 Rev 358
Line 116... Line 116...
//
//
// IF bypass 
// IF bypass 
//
//
assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
 
 
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                if_bypass_reg <=  1'b0;
                if_bypass_reg <=  1'b0;
        else
        else
                if_bypass_reg <=  if_bypass;
                if_bypass_reg <=  if_bypass;
 
 
//
//
Line 136... Line 136...
assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
 
 
//
//
// Flag for saved insn/address
// Flag for saved insn/address
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                saved <=  1'b0;
                saved <=  1'b0;
        else if (if_flushpipe)
        else if (if_flushpipe)
                saved <=  1'b0;
                saved <=  1'b0;
        else if (save_insn)
        else if (save_insn)
                saved <=  1'b1;
                saved <=  1'b1;
Line 149... Line 149...
                saved <=  1'b0;
                saved <=  1'b0;
 
 
//
//
// Store fetched instruction
// Store fetched instruction
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (if_flushpipe)
        else if (if_flushpipe)
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (save_insn)
        else if (save_insn)
                insn_saved <=  icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
                insn_saved <=  icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
Line 162... Line 162...
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
 
 
//
//
// Store fetched instruction's address
// Store fetched instruction's address
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                addr_saved <=  32'h00000000;
                addr_saved <=  32'h00000000;
        else if (if_flushpipe)
        else if (if_flushpipe)
                addr_saved <=  32'h00000000;
                addr_saved <=  32'h00000000;
        else if (save_insn)
        else if (save_insn)
                addr_saved <=  {icpu_adr_i[31:2], 2'b00};
                addr_saved <=  {icpu_adr_i[31:2], 2'b00};
Line 175... Line 175...
                addr_saved <=  {icpu_adr_i[31:2], 2'b00};
                addr_saved <=  {icpu_adr_i[31:2], 2'b00};
 
 
//
//
// Store fetched instruction's error tags 
// Store fetched instruction's error tags 
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                err_saved <=  3'b000;
                err_saved <=  3'b000;
        else if (if_flushpipe)
        else if (if_flushpipe)
                err_saved <=  3'b000;
                err_saved <=  3'b000;
        else if (save_insn) begin
        else if (save_insn) begin
                err_saved[0] <=  icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
                err_saved[0] <=  icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);

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