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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_immu_tlb.v] - Diff between revs 10 and 141

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Rev 10 Rev 141
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////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_immu_tlb.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Bugs fixed, coding style changed. 
 
//
 
// Revision 1.9  2004/06/08 18:17:36  lampret
 
// Non-functional changes. Coding style fixes.
 
//
// Revision 1.8  2004/04/05 08:29:57  lampret
// Revision 1.8  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
// Merged branch_qmem into main tree.
//
//
// Revision 1.6.4.1  2003/12/09 11:46:48  simons
// Revision 1.6.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
Line 204... Line 211...
 
 
//
//
// Output to SPRS unit
// Output to SPRS unit
//
//
assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
                        {vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
            {vpn, tlb_index, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
                (!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
                (!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
                        {ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
                        {ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
                        32'h00000000;
                        32'h00000000;
 
 
//
//
Line 254... Line 261...
 
 
 
 
//
//
// Instantiation of ITLB Match Registers
// Instantiation of ITLB Match Registers
//
//
or1200_spram_64x14 itlb_mr_ram(
   or1200_spram #
 
     (
 
      .aw(6),
 
      .dw(14)
 
      )
 
   itlb_mr_ram
 
     (
        .clk(clk),
        .clk(clk),
        .rst(rst),
 
`ifdef OR1200_BIST
`ifdef OR1200_BIST
        // RAM BIST
        // RAM BIST
        .mbist_si_i(itlb_mr_ram_si),
        .mbist_si_i(itlb_mr_ram_si),
        .mbist_so_o(itlb_mr_ram_so),
        .mbist_so_o(itlb_mr_ram_so),
        .mbist_ctrl_i(mbist_ctrl_i),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
`endif
        .ce(tlb_mr_en),
        .ce(tlb_mr_en),
        .we(tlb_mr_we),
        .we(tlb_mr_we),
        .oe(1'b1),
      //.oe(1'b1),
        .addr(tlb_index),
        .addr(tlb_index),
        .di(tlb_mr_ram_in),
        .di(tlb_mr_ram_in),
        .doq(tlb_mr_ram_out)
        .doq(tlb_mr_ram_out)
);
);
 
 
//
//
// Instantiation of ITLB Translate Registers
// Instantiation of ITLB Translate Registers
//
//
or1200_spram_64x22 itlb_tr_ram(
   or1200_spram #
 
     (
 
      .aw(6),
 
      .dw(22)
 
      )
 
   itlb_tr_ram
 
     (
        .clk(clk),
        .clk(clk),
        .rst(rst),
 
`ifdef OR1200_BIST
`ifdef OR1200_BIST
        // RAM BIST
        // RAM BIST
        .mbist_si_i(itlb_tr_ram_si),
        .mbist_si_i(itlb_tr_ram_si),
        .mbist_so_o(itlb_tr_ram_so),
        .mbist_so_o(itlb_tr_ram_so),
        .mbist_ctrl_i(mbist_ctrl_i),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
`endif
        .ce(tlb_tr_en),
        .ce(tlb_tr_en),
        .we(tlb_tr_we),
        .we(tlb_tr_we),
        .oe(1'b1),
      //.oe(1'b1),
        .addr(tlb_index),
        .addr(tlb_index),
        .di(tlb_tr_ram_in),
        .di(tlb_tr_ram_in),
        .doq(tlb_tr_ram_out)
        .doq(tlb_tr_ram_out)
);
);
 
 

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