| Line 249... |
Line 249... |
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//
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//
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// icpu_adr_o
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// icpu_adr_o
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge rst or posedge clk)
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always @(`OR1200_RST_EVENT rst or posedge clk)
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// default value
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// default value
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if (rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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icpu_adr_default <= 32'h0000_0100;
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icpu_adr_default <= 32'h0000_0100;
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icpu_adr_select <= 1'b1; // select async. value due to reset state
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icpu_adr_select <= 1'b1; // select async. value due to reset state
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end
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end
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// selected value (different from default) is written into FF after reset state
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// selected value (different from default) is written into FF after reset state
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else if (icpu_adr_select) begin
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else if (icpu_adr_select) begin
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| Line 288... |
Line 288... |
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//
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//
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
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// one clock cycle after offset part.
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// one clock cycle after offset part.
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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icpu_vpn_r <= {32-`OR1200_IMMU_PS{1'b0}};
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icpu_vpn_r <= {32-`OR1200_IMMU_PS{1'b0}};
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else
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else
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icpu_vpn_r <= icpu_adr_i[31:`OR1200_IMMU_PS];
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icpu_vpn_r <= icpu_adr_i[31:`OR1200_IMMU_PS];
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`ifdef OR1200_NO_IMMU
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`ifdef OR1200_NO_IMMU
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| Line 335... |
Line 335... |
//
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//
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// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
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// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
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// dis_spr_access_frst_clk sets dis_spr_access_scnd_clk and
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// dis_spr_access_frst_clk sets dis_spr_access_scnd_clk and
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// icpu_rty_o clears it.
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// icpu_rty_o clears it.
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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dis_spr_access_frst_clk <= 1'b0;
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dis_spr_access_frst_clk <= 1'b0;
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else if (!icpu_rty_o)
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else if (!icpu_rty_o)
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dis_spr_access_frst_clk <= 1'b0;
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dis_spr_access_frst_clk <= 1'b0;
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else if (spr_cs)
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else if (spr_cs)
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dis_spr_access_frst_clk <= 1'b1;
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dis_spr_access_frst_clk <= 1'b1;
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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dis_spr_access_scnd_clk <= 1'b0;
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dis_spr_access_scnd_clk <= 1'b0;
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else if (!icpu_rty_o)
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else if (!icpu_rty_o)
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dis_spr_access_scnd_clk <= 1'b0;
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dis_spr_access_scnd_clk <= 1'b0;
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else if (dis_spr_access_frst_clk)
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else if (dis_spr_access_frst_clk)
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dis_spr_access_scnd_clk <= 1'b1;
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dis_spr_access_scnd_clk <= 1'b1;
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| Line 375... |
Line 375... |
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//
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//
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// Assert itlb_en_r after one clock cycle and when there is no
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// Assert itlb_en_r after one clock cycle and when there is no
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// ITLB SPR access
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// ITLB SPR access
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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itlb_en_r <= 1'b0;
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itlb_en_r <= 1'b0;
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else
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else
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itlb_en_r <= itlb_en & ~itlb_spr_access;
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itlb_en_r <= itlb_en & ~itlb_spr_access;
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//
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//
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| Line 420... |
Line 420... |
//
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//
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// Output to SPRS unit
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// Output to SPRS unit
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//
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//
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// spr_dat_o is registered on the 1st clock of spr read
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// spr_dat_o is registered on the 1st clock of spr read
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// so itlb can continue with process during execution of mfspr.
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// so itlb can continue with process during execution of mfspr.
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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spr_dat_reg <= 32'h0000_0000;
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spr_dat_reg <= 32'h0000_0000;
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else if (spr_cs & !dis_spr_access_scnd_clk)
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else if (spr_cs & !dis_spr_access_scnd_clk)
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spr_dat_reg <= itlb_dat_o;
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spr_dat_reg <= itlb_dat_o;
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assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
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assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
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