OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Diff between revs 141 and 258

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 141 Rev 258
Line 252... Line 252...
//
//
`ifdef OR1200_REGISTERED_OUTPUTS
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge rst or posedge clk)
always @(posedge rst or posedge clk)
        // default value 
        // default value 
        if (rst) begin
        if (rst) begin
                icpu_adr_default <= #1 32'h0000_0100;
                icpu_adr_default <=  32'h0000_0100;
                icpu_adr_select  <= #1 1'b1;            // select async. value due to reset state
                icpu_adr_select  <=  1'b1;              // select async. value due to reset state
        end
        end
        // selected value (different from default) is written into FF after reset state
        // selected value (different from default) is written into FF after reset state
        else if (icpu_adr_select) begin
        else if (icpu_adr_select) begin
                icpu_adr_default <= #1 icpu_adr_boot;   // dynamic value can only be assigned to FF out of reset! 
                icpu_adr_default <=  icpu_adr_boot;     // dynamic value can only be assigned to FF out of reset! 
                icpu_adr_select  <= #1 1'b0;            // select FF value 
                icpu_adr_select  <=  1'b0;              // select FF value 
        end
        end
        else begin
        else begin
                icpu_adr_default <= #1 icpu_adr_i;
                icpu_adr_default <=  icpu_adr_i;
        end
        end
 
 
// select async. value for boot address after reset - PC jumps to the address selected after boot! 
// select async. value for boot address after reset - PC jumps to the address selected after boot! 
//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), 12'h100} ;
//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), 12'h100} ;
   assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
   assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
Line 290... Line 290...
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
// one clock cycle after offset part.
// one clock cycle after offset part.
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                icpu_vpn_r <= #1 {32-`OR1200_IMMU_PS{1'b0}};
                icpu_vpn_r <=  {32-`OR1200_IMMU_PS{1'b0}};
        else
        else
                icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS];
                icpu_vpn_r <=  icpu_adr_i[31:`OR1200_IMMU_PS];
 
 
`ifdef OR1200_NO_IMMU
`ifdef OR1200_NO_IMMU
 
 
//
//
// Put all outputs in inactive state
// Put all outputs in inactive state
Line 337... Line 337...
// dis_spr_access_frst_clk  sets dis_spr_access_scnd_clk and 
// dis_spr_access_frst_clk  sets dis_spr_access_scnd_clk and 
// icpu_rty_o clears it.
// icpu_rty_o clears it.
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dis_spr_access_frst_clk  <= #1 1'b0;
                dis_spr_access_frst_clk  <=  1'b0;
        else if (!icpu_rty_o)
        else if (!icpu_rty_o)
                dis_spr_access_frst_clk  <= #1 1'b0;
                dis_spr_access_frst_clk  <=  1'b0;
        else if (spr_cs)
        else if (spr_cs)
                dis_spr_access_frst_clk  <= #1 1'b1;
                dis_spr_access_frst_clk  <=  1'b1;
 
 
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                dis_spr_access_scnd_clk  <= #1 1'b0;
                dis_spr_access_scnd_clk  <=  1'b0;
        else if (!icpu_rty_o)
        else if (!icpu_rty_o)
                dis_spr_access_scnd_clk  <= #1 1'b0;
                dis_spr_access_scnd_clk  <=  1'b0;
        else if (dis_spr_access_frst_clk)
        else if (dis_spr_access_frst_clk)
                dis_spr_access_scnd_clk  <= #1 1'b1;
                dis_spr_access_scnd_clk  <=  1'b1;
 
 
//
//
// Tags:
// Tags:
//
//
// OR1200_ITAG_TE - TLB miss Exception
// OR1200_ITAG_TE - TLB miss Exception
Line 377... Line 377...
// Assert itlb_en_r after one clock cycle and when there is no
// Assert itlb_en_r after one clock cycle and when there is no
// ITLB SPR access
// ITLB SPR access
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                itlb_en_r <= #1 1'b0;
                itlb_en_r <=  1'b0;
        else
        else
                itlb_en_r <= #1 itlb_en & ~itlb_spr_access;
                itlb_en_r <=  itlb_en & ~itlb_spr_access;
 
 
//
//
// ITLB lookup successful
// ITLB lookup successful
//
//
assign itlb_done = itlb_en_r & ~page_cross;
assign itlb_done = itlb_en_r & ~page_cross;
Line 422... Line 422...
//
//
// spr_dat_o is registered on the 1st clock of spr read 
// spr_dat_o is registered on the 1st clock of spr read 
// so itlb can continue with process during execution of mfspr.
// so itlb can continue with process during execution of mfspr.
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                spr_dat_reg <= #1 32'h0000_0000;
                spr_dat_reg <=  32'h0000_0000;
        else if (spr_cs & !dis_spr_access_scnd_clk)
        else if (spr_cs & !dis_spr_access_scnd_clk)
                spr_dat_reg <= #1 itlb_dat_o;
                spr_dat_reg <=  itlb_dat_o;
 
 
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
 
 
//
//
// Page fault exception logic
// Page fault exception logic

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.