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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Diff between revs 258 and 358

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Rev 258 Rev 358
Line 249... Line 249...
 
 
//
//
// icpu_adr_o
// icpu_adr_o
//
//
`ifdef OR1200_REGISTERED_OUTPUTS
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge rst or posedge clk)
always @(`OR1200_RST_EVENT rst or posedge clk)
        // default value 
        // default value 
        if (rst) begin
        if (rst == `OR1200_RST_VALUE) begin
                icpu_adr_default <=  32'h0000_0100;
                icpu_adr_default <=  32'h0000_0100;
                icpu_adr_select  <=  1'b1;              // select async. value due to reset state
                icpu_adr_select  <=  1'b1;              // select async. value due to reset state
        end
        end
        // selected value (different from default) is written into FF after reset state
        // selected value (different from default) is written into FF after reset state
        else if (icpu_adr_select) begin
        else if (icpu_adr_select) begin
Line 288... Line 288...
 
 
//
//
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
// one clock cycle after offset part.
// one clock cycle after offset part.
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                icpu_vpn_r <=  {32-`OR1200_IMMU_PS{1'b0}};
                icpu_vpn_r <=  {32-`OR1200_IMMU_PS{1'b0}};
        else
        else
                icpu_vpn_r <=  icpu_adr_i[31:`OR1200_IMMU_PS];
                icpu_vpn_r <=  icpu_adr_i[31:`OR1200_IMMU_PS];
 
 
`ifdef OR1200_NO_IMMU
`ifdef OR1200_NO_IMMU
Line 335... Line 335...
//
//
// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
// dis_spr_access_frst_clk  sets dis_spr_access_scnd_clk and 
// dis_spr_access_frst_clk  sets dis_spr_access_scnd_clk and 
// icpu_rty_o clears it.
// icpu_rty_o clears it.
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                dis_spr_access_frst_clk  <=  1'b0;
                dis_spr_access_frst_clk  <=  1'b0;
        else if (!icpu_rty_o)
        else if (!icpu_rty_o)
                dis_spr_access_frst_clk  <=  1'b0;
                dis_spr_access_frst_clk  <=  1'b0;
        else if (spr_cs)
        else if (spr_cs)
                dis_spr_access_frst_clk  <=  1'b1;
                dis_spr_access_frst_clk  <=  1'b1;
 
 
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                dis_spr_access_scnd_clk  <=  1'b0;
                dis_spr_access_scnd_clk  <=  1'b0;
        else if (!icpu_rty_o)
        else if (!icpu_rty_o)
                dis_spr_access_scnd_clk  <=  1'b0;
                dis_spr_access_scnd_clk  <=  1'b0;
        else if (dis_spr_access_frst_clk)
        else if (dis_spr_access_frst_clk)
                dis_spr_access_scnd_clk  <=  1'b1;
                dis_spr_access_scnd_clk  <=  1'b1;
Line 375... Line 375...
 
 
//
//
// Assert itlb_en_r after one clock cycle and when there is no
// Assert itlb_en_r after one clock cycle and when there is no
// ITLB SPR access
// ITLB SPR access
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                itlb_en_r <=  1'b0;
                itlb_en_r <=  1'b0;
        else
        else
                itlb_en_r <=  itlb_en & ~itlb_spr_access;
                itlb_en_r <=  itlb_en & ~itlb_spr_access;
 
 
//
//
Line 420... Line 420...
//
//
// Output to SPRS unit
// Output to SPRS unit
//
//
// spr_dat_o is registered on the 1st clock of spr read 
// spr_dat_o is registered on the 1st clock of spr read 
// so itlb can continue with process during execution of mfspr.
// so itlb can continue with process during execution of mfspr.
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                spr_dat_reg <=  32'h0000_0000;
                spr_dat_reg <=  32'h0000_0000;
        else if (spr_cs & !dis_spr_access_scnd_clk)
        else if (spr_cs & !dis_spr_access_scnd_clk)
                spr_dat_reg <=  itlb_dat_o;
                spr_dat_reg <=  itlb_dat_o;
 
 
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;

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