OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_iwb_biu.v] - Diff between revs 141 and 258

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 141 Rev 258
Line 1... Line 1...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  OR1200's WISHBONE BIU                                       ////
////  OR1200's WISHBONE BIU                                       ////
////                                                              ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////  http://opencores.org/project,or1k                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Implements WISHBONE interface                               ////
////  Implements WISHBONE interface                               ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
Line 44... Line 44...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
 
//
 
// $Log: or1200_iwb_biu.v,v $
// $Log: or1200_iwb_biu.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Major update: 
// This module is obsolete.
// This module is obsolete.
//
//
// Revision 1.2  2004/04/05 08:29:57  lampret
 
// Merged branch_qmem into main tree.
 
//
 
// Revision 1.1  2003/12/05 00:12:08  lampret
 
// New wb_biu for iwb interface.
 
//
 
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
 
// Added embedded memory QMEM.
 
//
 
// Revision 1.6  2003/04/07 20:57:46  lampret
 
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
 
//
 
// Revision 1.5  2002/12/08 08:57:56  lampret
 
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
 
//
 
// Revision 1.4  2002/09/16 03:09:16  lampret
 
// Fixed a combinational loop.
 
//
 
// Revision 1.3  2002/08/12 05:31:37  lampret
 
// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
 
//
 
// Revision 1.2  2002/07/14 22:17:17  lampret
 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
 
//
 
// Revision 1.1  2002/01/03 08:16:15  lampret
 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
 
//
 
// Revision 1.12  2001/11/22 13:42:51  lampret
 
// Added wb_cyc_o assignment after it was removed by accident.
 
//
 
// Revision 1.11  2001/11/20 21:28:10  lampret
 
// Added optional sampling of inputs.
 
//
 
// Revision 1.10  2001/11/18 11:32:00  lampret
 
// OR1200_REGISTERED_OUTPUTS can now be enabled.
 
//
 
// Revision 1.9  2001/10/21 17:57:16  lampret
 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
 
//
 
// Revision 1.8  2001/10/14 13:12:10  lampret
 
// MP3 version.
 
//
 
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
 
// no message
 
//
 
// Revision 1.3  2001/08/09 13:39:33  lampret
 
// Major clean-up.
 
//
 
// Revision 1.2  2001/07/22 03:31:54  lampret
 
// Fixed RAM's oen bug. Cache bypass under development.
 
//
 
// Revision 1.1  2001/07/20 00:46:23  lampret
 
// Development version of RTL. Libraries are missing.
 
//
 
//
 
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.