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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Load/Store unit ////
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//// OR1200's Load/Store unit ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Interface between CPU and DC. ////
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//// Interface between CPU and DC. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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//
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// $Log: or1200_lsu.v,v $
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// $Log: or1200_lsu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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//
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//
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// Revision 1.5 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.4 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.3 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9 2001/11/30 18:59:47 simons
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// *** empty log message ***
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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//
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//
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// ex_lsu_op
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// ex_lsu_op
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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ex_lsu_op <= #1 `OR1200_LSUOP_NOP;
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ex_lsu_op <= `OR1200_LSUOP_NOP;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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ex_lsu_op <= #1 `OR1200_LSUOP_NOP;
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ex_lsu_op <= `OR1200_LSUOP_NOP;
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else if (!ex_freeze)
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else if (!ex_freeze)
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ex_lsu_op <= #1 id_lsu_op;
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ex_lsu_op <= id_lsu_op;
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end
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end
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//
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//
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// Precalculate part of load/store EA in ID stage
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// Precalculate part of load/store EA in ID stage
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//
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//
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assign id_precalc_sum = id_addrbase[`OR1200_LSUEA_PRECALC-1:0] +
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assign id_precalc_sum = id_addrbase[`OR1200_LSUEA_PRECALC-1:0] +
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id_addrofs[`OR1200_LSUEA_PRECALC-1:0];
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id_addrofs[`OR1200_LSUEA_PRECALC-1:0];
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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dcpu_adr_r <= #1 {`OR1200_LSUEA_PRECALC{1'b0}};
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dcpu_adr_r <= {`OR1200_LSUEA_PRECALC{1'b0}};
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else if (!ex_freeze)
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else if (!ex_freeze)
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dcpu_adr_r <= #1 id_precalc_sum;
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dcpu_adr_r <= id_precalc_sum;
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end
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end
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//
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//
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// Generate except_align in ID stage
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// Generate except_align in ID stage
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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except_align <= #1 1'b0;
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except_align <= 1'b0;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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except_align <= #1 1'b0;
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except_align <= 1'b0;
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else if (!ex_freeze)
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else if (!ex_freeze)
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except_align <= #1 ((id_lsu_op == `OR1200_LSUOP_SH) |
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except_align <= ((id_lsu_op == `OR1200_LSUOP_SH) |
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(id_lsu_op == `OR1200_LSUOP_LHZ) |
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(id_lsu_op == `OR1200_LSUOP_LHZ) |
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(id_lsu_op == `OR1200_LSUOP_LHS)) & id_precalc_sum[0]
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(id_lsu_op == `OR1200_LSUOP_LHS)) & id_precalc_sum[0]
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| ((id_lsu_op == `OR1200_LSUOP_SW) |
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| ((id_lsu_op == `OR1200_LSUOP_SW) |
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(id_lsu_op == `OR1200_LSUOP_LWZ) |
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(id_lsu_op == `OR1200_LSUOP_LWZ) |
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(id_lsu_op == `OR1200_LSUOP_LWS)) & |id_precalc_sum[1:0];
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(id_lsu_op == `OR1200_LSUOP_LWS)) & |id_precalc_sum[1:0];
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assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
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assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
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//
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//
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// External I/F assignments
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// External I/F assignments
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//
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//
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assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] = ex_addrbase[31:`OR1200_LSUEA_PRECALC] +
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assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] = ex_addrbase[31:`OR1200_LSUEA_PRECALC] + ex_addrofs[31:`OR1200_LSUEA_PRECALC] + dcpu_adr_r[`OR1200_LSUEA_PRECALC]; // carry
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ex_addrofs[31:`OR1200_LSUEA_PRECALC] +
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dcpu_adr_r[`OR1200_LSUEA_PRECALC]; // carry
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assign dcpu_adr_o[`OR1200_LSUEA_PRECALC-1:0] = dcpu_adr_r[`OR1200_LSUEA_PRECALC-1:0];
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assign dcpu_adr_o[`OR1200_LSUEA_PRECALC-1:0] = dcpu_adr_r[`OR1200_LSUEA_PRECALC-1:0];
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assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |ex_lsu_op;
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assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ?
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1'b0 : |ex_lsu_op;
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assign dcpu_we_o = ex_lsu_op[3];
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assign dcpu_we_o = ex_lsu_op[3];
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assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
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assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
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always @(ex_lsu_op or dcpu_adr_o)
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always @(ex_lsu_op or dcpu_adr_o)
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casex({ex_lsu_op, dcpu_adr_o[1:0]})
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casex({ex_lsu_op, dcpu_adr_o[1:0]})
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{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
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