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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_lsu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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//
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// Revision 1.5 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.4 2002/03/29 15:16:56 lampret
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// Revision 1.4 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.3 2002/02/11 04:33:17 lampret
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// Revision 1.3 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_lsu(
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module or1200_lsu(
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// Clock and Reset
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clk, rst,
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// Internal i/f
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// Internal i/f
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addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
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id_addrbase, ex_addrbase, id_addrofs, ex_addrofs, id_lsu_op,
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lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
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du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
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du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
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id_freeze, ex_freeze, flushpipe,
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// External i/f to DC
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// External i/f to DC
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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//
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//
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// Clock and reset
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//
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input clk;
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input rst;
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input [31:0] addrbase;
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input [31:0] id_addrbase;
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input [31:0] addrofs;
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input [31:0] ex_addrbase;
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input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
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input [31:0] id_addrofs;
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input [31:0] ex_addrofs;
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input [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
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input [dw-1:0] lsu_datain;
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input [dw-1:0] lsu_datain;
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output [dw-1:0] lsu_dataout;
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output [dw-1:0] lsu_dataout;
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output lsu_stall;
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output lsu_stall;
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output lsu_unstall;
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output lsu_unstall;
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input du_stall;
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input du_stall;
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output except_align;
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output except_align;
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output except_dtlbmiss;
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output except_dtlbmiss;
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output except_dmmufault;
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output except_dmmufault;
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output except_dbuserr;
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output except_dbuserr;
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input id_freeze;
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input ex_freeze;
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input flushpipe;
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//
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//
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// External i/f to DC
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// External i/f to DC
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//
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//
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output [31:0] dcpu_adr_o;
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output [31:0] dcpu_adr_o;
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//
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//
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// Internal wires/regs
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// Internal wires/regs
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//
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//
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reg [3:0] dcpu_sel_o;
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reg [3:0] dcpu_sel_o;
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reg [`OR1200_LSUOP_WIDTH-1:0] ex_lsu_op;
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wire [`OR1200_LSUEA_PRECALC:0] id_precalc_sum;
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reg [`OR1200_LSUEA_PRECALC:0] dcpu_adr_r;
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reg except_align;
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//
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// ex_lsu_op
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//
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always @(posedge clk or posedge rst) begin
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if (rst)
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ex_lsu_op <= #1 `OR1200_LSUOP_NOP;
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else if (!ex_freeze & id_freeze | flushpipe)
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ex_lsu_op <= #1 `OR1200_LSUOP_NOP;
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else if (!ex_freeze)
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ex_lsu_op <= #1 id_lsu_op;
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end
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//
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// Precalculate part of load/store EA in ID stage
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//
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assign id_precalc_sum = id_addrbase[`OR1200_LSUEA_PRECALC-1:0] +
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id_addrofs[`OR1200_LSUEA_PRECALC-1:0];
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always @(posedge clk or posedge rst) begin
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if (rst)
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dcpu_adr_r <= #1 {`OR1200_LSUEA_PRECALC{1'b0}};
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else if (!ex_freeze)
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dcpu_adr_r <= #1 id_precalc_sum;
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end
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//
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// Generate except_align in ID stage
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//
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always @(posedge clk or posedge rst) begin
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if (rst)
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except_align <= #1 1'b0;
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else if (!ex_freeze & id_freeze | flushpipe)
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except_align <= #1 1'b0;
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else if (!ex_freeze)
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except_align <= #1 ((id_lsu_op == `OR1200_LSUOP_SH) |
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(id_lsu_op == `OR1200_LSUOP_LHZ) |
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(id_lsu_op == `OR1200_LSUOP_LHS)) & id_precalc_sum[0]
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| ((id_lsu_op == `OR1200_LSUOP_SW) |
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(id_lsu_op == `OR1200_LSUOP_LWZ) |
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(id_lsu_op == `OR1200_LSUOP_LWS)) & |id_precalc_sum[1:0];
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end
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//
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//
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// Internal I/F assignments
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// Internal I/F assignments
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//
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//
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assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
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assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
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assign lsu_unstall = dcpu_ack_i;
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assign lsu_unstall = dcpu_ack_i;
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assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0]
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| ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0];
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assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
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assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
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assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
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assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
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assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
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assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
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//
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//
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// External I/F assignments
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// External I/F assignments
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//
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//
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assign dcpu_adr_o = addrbase + addrofs;
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assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] = ex_addrbase[31:`OR1200_LSUEA_PRECALC] +
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assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |lsu_op;
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ex_addrofs[31:`OR1200_LSUEA_PRECALC] +
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assign dcpu_we_o = lsu_op[3];
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dcpu_adr_r[`OR1200_LSUEA_PRECALC]; // carry
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assign dcpu_adr_o[`OR1200_LSUEA_PRECALC-1:0] = dcpu_adr_r[`OR1200_LSUEA_PRECALC-1:0];
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assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |ex_lsu_op;
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assign dcpu_we_o = ex_lsu_op[3];
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assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
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assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
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always @(lsu_op or dcpu_adr_o)
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always @(ex_lsu_op or dcpu_adr_o)
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casex({lsu_op, dcpu_adr_o[1:0]})
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casex({ex_lsu_op, dcpu_adr_o[1:0]})
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{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
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{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
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{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
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{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
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{`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
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{`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
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{`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
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{`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
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//
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//
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// Instantiation of Memory-to-regfile aligner
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// Instantiation of Memory-to-regfile aligner
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//
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//
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or1200_mem2reg or1200_mem2reg(
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or1200_mem2reg or1200_mem2reg(
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.addr(dcpu_adr_o[1:0]),
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.addr(dcpu_adr_o[1:0]),
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.lsu_op(lsu_op),
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.lsu_op(ex_lsu_op),
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.memdata(dcpu_dat_i),
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.memdata(dcpu_dat_i),
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.regdata(lsu_dataout)
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.regdata(lsu_dataout)
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);
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);
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//
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//
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// Instantiation of Regfile-to-memory aligner
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// Instantiation of Regfile-to-memory aligner
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//
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//
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or1200_reg2mem or1200_reg2mem(
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or1200_reg2mem or1200_reg2mem(
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.addr(dcpu_adr_o[1:0]),
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.addr(dcpu_adr_o[1:0]),
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.lsu_op(lsu_op),
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.lsu_op(ex_lsu_op),
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.regdata(lsu_datain),
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.regdata(lsu_datain),
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.memdata(dcpu_dat_o)
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.memdata(dcpu_dat_o)
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);
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);
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endmodule
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endmodule
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