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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mem2reg.v] - Diff between revs 10 and 141

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Rev 10 Rev 141
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// CVS Revision History
// CVS Revision History
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//
// $Log: not supported by cvs2svn $
// $Log: or1200_mem2reg.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// No update 
 
//
 
// Revision 1.5  2002/09/03 22:28:21  lampret
 
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
 
//
// Revision 1.4  2002/03/29 15:16:56  lampret
// Revision 1.4  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
// Some of the warnings fixed.
//
//
// Revision 1.3  2002/03/28 19:14:10  lampret
// Revision 1.3  2002/03/28 19:14:10  lampret
// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2

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