OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Diff between revs 258 and 356

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 258 Rev 356
Line 115... Line 115...
`ifdef OR1200_MAC_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r1;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r1;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r2;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r2;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r3;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r3;
reg                             mac_stall_r;
reg                             mac_stall_r;
reg     [2*width-1:0]            mac_r;
reg     [63:0]           mac_r;
`else
`else
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op_r1;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op_r1;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op_r2;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op_r2;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op_r3;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op_r3;
wire                            mac_stall_r;
wire                            mac_stall_r;
wire    [2*width-1:0]            mac_r;
wire    [63:0]           mac_r;
`endif
`endif
wire    [width-1:0]              x;
wire    [width-1:0]              x;
wire    [width-1:0]              y;
wire    [width-1:0]              y;
wire                            spr_maclo_we;
wire                            spr_maclo_we;
wire                            spr_machi_we;
wire                            spr_machi_we;
Line 173... Line 173...
 
 
//
//
// Select result of current ALU operation to be forwarded
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
// to next instruction and to WB stage
//
//
always @(alu_op or mul_prod_r or mac_r or a or b)
always @*
  casex(alu_op) // synopsys parallel_case
  casex(alu_op) // synopsys parallel_case
 `ifdef OR1200_DIV_IMPLEMENTED
 `ifdef OR1200_DIV_IMPLEMENTED
    `OR1200_ALUOP_DIV: begin
    `OR1200_ALUOP_DIV: begin
       result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
       result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
    end
    end
Line 251... Line 251...
assign mul_prod = {2*width{1'b0}};
assign mul_prod = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
`endif // OR1200_MULT_IMPLEMENTED
`endif // OR1200_MULT_IMPLEMENTED
 
 
`ifdef OR1200_MAC_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
 
// Signal to indicate when we should check for new MAC op
 
reg ex_freeze_r;
 
 
 
always @(posedge clk or posedge rst)
 
  if (rst)
 
    ex_freeze_r <= 1'b1;
 
  else
 
    ex_freeze_r <= ex_freeze;
 
 
//
//
// Propagation of l.mac opcode
// Propagation of l.mac opcode, only register it for one cycle
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                mac_op_r1 <=  `OR1200_MACOP_WIDTH'b0;
                mac_op_r1 <=  `OR1200_MACOP_WIDTH'b0;
        else
        else
                mac_op_r1 <=  mac_op;
                mac_op_r1 <=  !ex_freeze_r ? mac_op : `OR1200_MACOP_WIDTH'b0;
 
 
//
//
// Propagation of l.mac opcode
// Propagation of l.mac opcode
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.