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Line 115... |
`ifdef OR1200_MAC_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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reg mac_stall_r;
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reg mac_stall_r;
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reg [2*width-1:0] mac_r;
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reg [63:0] mac_r;
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`else
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`else
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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wire mac_stall_r;
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wire mac_stall_r;
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wire [2*width-1:0] mac_r;
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wire [63:0] mac_r;
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`endif
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`endif
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wire [width-1:0] x;
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wire [width-1:0] x;
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wire [width-1:0] y;
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wire [width-1:0] y;
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wire spr_maclo_we;
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wire spr_maclo_we;
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wire spr_machi_we;
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wire spr_machi_we;
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Line 173... |
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//
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//
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// Select result of current ALU operation to be forwarded
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// Select result of current ALU operation to be forwarded
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// to next instruction and to WB stage
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// to next instruction and to WB stage
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//
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//
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always @(alu_op or mul_prod_r or mac_r or a or b)
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always @*
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casex(alu_op) // synopsys parallel_case
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casex(alu_op) // synopsys parallel_case
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`ifdef OR1200_DIV_IMPLEMENTED
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`ifdef OR1200_DIV_IMPLEMENTED
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`OR1200_ALUOP_DIV: begin
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`OR1200_ALUOP_DIV: begin
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result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
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result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
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end
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end
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assign mul_prod = {2*width{1'b0}};
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assign mul_prod = {2*width{1'b0}};
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assign mul_prod_r = {2*width{1'b0}};
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assign mul_prod_r = {2*width{1'b0}};
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`endif // OR1200_MULT_IMPLEMENTED
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`endif // OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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// Signal to indicate when we should check for new MAC op
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reg ex_freeze_r;
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always @(posedge clk or posedge rst)
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if (rst)
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ex_freeze_r <= 1'b1;
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else
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ex_freeze_r <= ex_freeze;
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//
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//
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// Propagation of l.mac opcode
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// Propagation of l.mac opcode, only register it for one cycle
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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mac_op_r1 <= `OR1200_MACOP_WIDTH'b0;
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mac_op_r1 <= `OR1200_MACOP_WIDTH'b0;
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else
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else
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mac_op_r1 <= mac_op;
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mac_op_r1 <= !ex_freeze_r ? mac_op : `OR1200_MACOP_WIDTH'b0;
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//
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//
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// Propagation of l.mac opcode
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// Propagation of l.mac opcode
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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