| Line 217... |
Line 217... |
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//
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//
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// Registered output from the multiplier and
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// Registered output from the multiplier and
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// an optional divider
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// an optional divider
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//
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//
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always @(posedge rst or posedge clk)
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always @(`OR1200_RST_EVENT rst or posedge clk)
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if (rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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mul_prod_r <= 64'h0000_0000_0000_0000;
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mul_prod_r <= 64'h0000_0000_0000_0000;
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div_free <= 1'b1;
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div_free <= 1'b1;
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`ifdef OR1200_DIV_IMPLEMENTED
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`ifdef OR1200_DIV_IMPLEMENTED
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div_cntr <= 6'b00_0000;
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div_cntr <= 6'b00_0000;
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`endif
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`endif
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| Line 254... |
Line 254... |
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`ifdef OR1200_MAC_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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// Signal to indicate when we should check for new MAC op
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// Signal to indicate when we should check for new MAC op
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reg ex_freeze_r;
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reg ex_freeze_r;
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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ex_freeze_r <= 1'b1;
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ex_freeze_r <= 1'b1;
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else
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else
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ex_freeze_r <= ex_freeze;
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ex_freeze_r <= ex_freeze;
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//
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//
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// Propagation of l.mac opcode, only register it for one cycle
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// Propagation of l.mac opcode, only register it for one cycle
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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mac_op_r1 <= `OR1200_MACOP_WIDTH'b0;
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mac_op_r1 <= `OR1200_MACOP_WIDTH'b0;
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else
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else
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mac_op_r1 <= !ex_freeze_r ? mac_op : `OR1200_MACOP_WIDTH'b0;
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mac_op_r1 <= !ex_freeze_r ? mac_op : `OR1200_MACOP_WIDTH'b0;
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//
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//
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// Propagation of l.mac opcode
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// Propagation of l.mac opcode
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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mac_op_r2 <= `OR1200_MACOP_WIDTH'b0;
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mac_op_r2 <= `OR1200_MACOP_WIDTH'b0;
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else
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else
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mac_op_r2 <= mac_op_r1;
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mac_op_r2 <= mac_op_r1;
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//
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//
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// Propagation of l.mac opcode
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// Propagation of l.mac opcode
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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mac_op_r3 <= `OR1200_MACOP_WIDTH'b0;
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mac_op_r3 <= `OR1200_MACOP_WIDTH'b0;
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else
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else
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mac_op_r3 <= mac_op_r2;
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mac_op_r3 <= mac_op_r2;
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//
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//
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// Implementation of MAC
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// Implementation of MAC
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//
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//
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always @(posedge rst or posedge clk)
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always @(`OR1200_RST_EVENT rst or posedge clk)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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mac_r <= 64'h0000_0000_0000_0000;
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mac_r <= 64'h0000_0000_0000_0000;
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`ifdef OR1200_MAC_SPR_WE
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`ifdef OR1200_MAC_SPR_WE
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else if (spr_maclo_we)
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else if (spr_maclo_we)
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mac_r[31:0] <= spr_dat_i;
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mac_r[31:0] <= spr_dat_i;
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else if (spr_machi_we)
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else if (spr_machi_we)
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| Line 311... |
Line 311... |
//
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//
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// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
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// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
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// in EX stage (e.g. inside multiplier)
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// in EX stage (e.g. inside multiplier)
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// This stall signal is also used by the divider.
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// This stall signal is also used by the divider.
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//
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//
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always @(posedge rst or posedge clk)
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always @(`OR1200_RST_EVENT rst or posedge clk)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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mac_stall_r <= 1'b0;
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mac_stall_r <= 1'b0;
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else
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else
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mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & (id_macrc_op | mac_stall_r)
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mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & (id_macrc_op | mac_stall_r)
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`ifdef OR1200_DIV_IMPLEMENTED
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`ifdef OR1200_DIV_IMPLEMENTED
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| (|div_cntr)
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| (|div_cntr)
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