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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Diff between revs 358 and 364

Rev 358	Rev 364
Line 174...	Line 174...
`//`	`//`
`// Select result of current ALU operation to be forwarded`	`// Select result of current ALU operation to be forwarded`
`// to next instruction and to WB stage`	`// to next instruction and to WB stage`
`//`	`//`
`always @*`	`always @*`
`casex(alu_op) // synopsys parallel_case`	`casez(alu_op) // synopsys parallel_case`
`ifdef OR1200_DIV_IMPLEMENTED	`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIV: begin	`OR1200_ALUOP_DIV: begin
`result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];`	`result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 32'd1 : mul_prod_r[31:0];`
`end`	`end`
`OR1200_ALUOP_DIVU,	`OR1200_ALUOP_DIVU,
`endif	`endif
`OR1200_ALUOP_MUL: begin	`OR1200_ALUOP_MUL: begin
`result = mul_prod_r[31:0];`	`result = mul_prod_r[31:0];`
Line 231...	Line 231...
`else if (\|div_cntr) begin`	`else if (\|div_cntr) begin`
`if (div_tmp[31])`	`if (div_tmp[31])`
`mul_prod_r <= {mul_prod_r[62:0], 1'b0};`	`mul_prod_r <= {mul_prod_r[62:0], 1'b0};`
`else`	`else`
`mul_prod_r <= {div_tmp[30:0], mul_prod_r[31:0], 1'b1};`	`mul_prod_r <= {div_tmp[30:0], mul_prod_r[31:0], 1'b1};`
`div_cntr <= div_cntr - 1'b1;`	`div_cntr <= div_cntr - 6'd1;`
`end`	`end`
`else if (alu_op_div_divu && div_free) begin`	`else if (alu_op_div_divu && div_free) begin`
`mul_prod_r <= {31'b0, x[31:0], 1'b0};`	`mul_prod_r <= {31'b0, x[31:0], 1'b0};`
`div_cntr <= 6'b10_0000;`	`div_cntr <= 6'b10_0000;`
`div_free <= 1'b0;`	`div_free <= 1'b0;`