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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Diff between revs 481 and 640

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Rev 481 Rev 640
Line 105... Line 105...
 
 
   //
   //
   // Internal wires and regs
   // Internal wires and regs
   //
   //
   reg [width-1:0]                       result;
   reg [width-1:0]                       result;
 
   reg                                  ex_freeze_r;
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MULT_IMPLEMENTED
   reg [2*width-1:0]                     mul_prod_r;
   reg [2*width-1:0]                     mul_prod_r;
   wire                                 alu_op_smul;
   wire                                 alu_op_smul;
   wire                                 alu_op_umul;
   wire                                 alu_op_umul;
   wire                                 alu_op_mul;
   wire                                 alu_op_mul;
Line 119... Line 120...
`else
`else
   wire [2*width-1:0]                    mul_prod_r;
   wire [2*width-1:0]                    mul_prod_r;
`endif
`endif
   wire [2*width-1:0]                    mul_prod;
   wire [2*width-1:0]                    mul_prod;
   wire                                 mul_stall;
   wire                                 mul_stall;
 
   reg [1:0]                             mul_stall_count;
   wire [`OR1200_MACOP_WIDTH-1:0]        mac_op;
   wire [`OR1200_MACOP_WIDTH-1:0]        mac_op;
`ifdef OR1200_MAC_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
   reg [`OR1200_MACOP_WIDTH-1:0]         mac_op_r1;
   reg [`OR1200_MACOP_WIDTH-1:0]         mac_op_r1;
   reg [`OR1200_MACOP_WIDTH-1:0]         mac_op_r2;
   reg [`OR1200_MACOP_WIDTH-1:0]         mac_op_r2;
   reg [`OR1200_MACOP_WIDTH-1:0]         mac_op_r3;
   reg [`OR1200_MACOP_WIDTH-1:0]         mac_op_r3;
Line 186... Line 187...
   assign x = (alu_op_sdiv | alu_op_smul) & a[31] ? ~a + 32'b1 :
   assign x = (alu_op_sdiv | alu_op_smul) & a[31] ? ~a + 32'b1 :
              alu_op_div | alu_op_mul | (|mac_op) ? a : 32'd0;
              alu_op_div | alu_op_mul | (|mac_op) ? a : 32'd0;
   assign y = (alu_op_sdiv | alu_op_smul) & b[31] ? ~b + 32'b1 :
   assign y = (alu_op_sdiv | alu_op_smul) & b[31] ? ~b + 32'b1 :
              alu_op_div | alu_op_mul | (|mac_op) ? b : 32'd0;
              alu_op_div | alu_op_mul | (|mac_op) ? b : 32'd0;
 
 
 
   // Used to indicate when we should check for new multiply or MAC ops
 
   always @(posedge clk or `OR1200_RST_EVENT rst)
 
     if (rst == `OR1200_RST_VALUE)
 
       ex_freeze_r <= 1'b1;
 
     else
 
       ex_freeze_r <= ex_freeze;
 
 
   //
   //
   // Select result of current ALU operation to be forwarded
   // Select result of current ALU operation to be forwarded
   // to next instruction and to WB stage
   // to next instruction and to WB stage
   //
   //
   always @*
   always @*
Line 285... Line 293...
     end
     end
     else begin
     else begin
        mul_prod_r <=  mul_prod[63:0];
        mul_prod_r <=  mul_prod[63:0];
     end
     end
 
 
   assign mul_stall = 0;
   //
 
   // Generate stall signal during multiplication
 
   //
 
   always @(`OR1200_RST_EVENT rst or posedge clk)
 
     if (rst == `OR1200_RST_VALUE)
 
       mul_stall_count <= 0;
 
     else if (!(|mul_stall_count))
 
       mul_stall_count <= {mul_stall_count[0], alu_op_mul & !ex_freeze_r};
 
     else
 
       mul_stall_count <= {mul_stall_count[0],1'b0};
 
 
 
   assign mul_stall = (|mul_stall_count) |
 
                      (!(|mul_stall_count) & alu_op_mul & !ex_freeze_r);
 
 
 `endif // !`ifdef OR1200_MULT_SERIAL   
 `endif // !`ifdef OR1200_MULT_SERIAL   
 
 
`else // OR1200_MULT_IMPLEMENTED
`else // OR1200_MULT_IMPLEMENTED
   assign mul_prod = {2*width{1'b0}};
   assign mul_prod = {2*width{1'b0}};
   assign mul_prod_r = {2*width{1'b0}};
   assign mul_prod_r = {2*width{1'b0}};
   assign mul_stall = 0;
   assign mul_stall = 0;
`endif // OR1200_MULT_IMPLEMENTED
`endif // OR1200_MULT_IMPLEMENTED
 
 
`ifdef OR1200_MAC_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
   // Signal to indicate when we should check for new MAC op
 
   reg ex_freeze_r;
 
 
 
   always @(posedge clk or `OR1200_RST_EVENT rst)
 
     if (rst == `OR1200_RST_VALUE)
 
       ex_freeze_r <= 1'b1;
 
     else
 
       ex_freeze_r <= ex_freeze;
 
 
 
   //
   //
   // Propagation of l.mac opcode, only register it for one cycle
   // Propagation of l.mac opcode, only register it for one cycle
   //
   //
   always @(posedge clk or `OR1200_RST_EVENT rst)
   always @(posedge clk or `OR1200_RST_EVENT rst)
Line 361... Line 374...
     if (rst == `OR1200_RST_VALUE)
     if (rst == `OR1200_RST_VALUE)
       mac_stall_r <=  1'b0;
       mac_stall_r <=  1'b0;
     else
     else
       mac_stall_r <=  (|mac_op | (|mac_op_r1) | (|mac_op_r2)) &
       mac_stall_r <=  (|mac_op | (|mac_op_r1) | (|mac_op_r2)) &
                       (id_macrc_op | mac_stall_r);
                       (id_macrc_op | mac_stall_r);
 
 
`else // OR1200_MAC_IMPLEMENTED
`else // OR1200_MAC_IMPLEMENTED
   assign mac_stall_r = 1'b0;
   assign mac_stall_r = 1'b0;
   assign mac_r = {2*width{1'b0}};
   assign mac_r = {2*width{1'b0}};
   assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
   assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
   assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
   assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;

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