| Line 105... |
Line 105... |
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [width-1:0] result;
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reg [width-1:0] result;
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reg ex_freeze_r;
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`ifdef OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MULT_IMPLEMENTED
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reg [2*width-1:0] mul_prod_r;
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reg [2*width-1:0] mul_prod_r;
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wire alu_op_smul;
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wire alu_op_smul;
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wire alu_op_umul;
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wire alu_op_umul;
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wire alu_op_mul;
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wire alu_op_mul;
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| Line 119... |
Line 120... |
`else
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`else
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wire [2*width-1:0] mul_prod_r;
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wire [2*width-1:0] mul_prod_r;
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`endif
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`endif
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wire [2*width-1:0] mul_prod;
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wire [2*width-1:0] mul_prod;
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wire mul_stall;
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wire mul_stall;
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reg [1:0] mul_stall_count;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
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`ifdef OR1200_MAC_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
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| Line 186... |
Line 187... |
assign x = (alu_op_sdiv | alu_op_smul) & a[31] ? ~a + 32'b1 :
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assign x = (alu_op_sdiv | alu_op_smul) & a[31] ? ~a + 32'b1 :
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alu_op_div | alu_op_mul | (|mac_op) ? a : 32'd0;
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alu_op_div | alu_op_mul | (|mac_op) ? a : 32'd0;
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assign y = (alu_op_sdiv | alu_op_smul) & b[31] ? ~b + 32'b1 :
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assign y = (alu_op_sdiv | alu_op_smul) & b[31] ? ~b + 32'b1 :
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alu_op_div | alu_op_mul | (|mac_op) ? b : 32'd0;
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alu_op_div | alu_op_mul | (|mac_op) ? b : 32'd0;
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// Used to indicate when we should check for new multiply or MAC ops
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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ex_freeze_r <= 1'b1;
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else
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ex_freeze_r <= ex_freeze;
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//
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//
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// Select result of current ALU operation to be forwarded
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// Select result of current ALU operation to be forwarded
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// to next instruction and to WB stage
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// to next instruction and to WB stage
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//
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//
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always @*
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always @*
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| Line 285... |
Line 293... |
end
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end
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else begin
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else begin
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mul_prod_r <= mul_prod[63:0];
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mul_prod_r <= mul_prod[63:0];
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end
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end
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assign mul_stall = 0;
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//
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// Generate stall signal during multiplication
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//
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always @(`OR1200_RST_EVENT rst or posedge clk)
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if (rst == `OR1200_RST_VALUE)
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mul_stall_count <= 0;
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else if (!(|mul_stall_count))
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mul_stall_count <= {mul_stall_count[0], alu_op_mul & !ex_freeze_r};
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else
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mul_stall_count <= {mul_stall_count[0],1'b0};
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assign mul_stall = (|mul_stall_count) |
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(!(|mul_stall_count) & alu_op_mul & !ex_freeze_r);
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`endif // !`ifdef OR1200_MULT_SERIAL
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`endif // !`ifdef OR1200_MULT_SERIAL
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`else // OR1200_MULT_IMPLEMENTED
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`else // OR1200_MULT_IMPLEMENTED
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assign mul_prod = {2*width{1'b0}};
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assign mul_prod = {2*width{1'b0}};
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assign mul_prod_r = {2*width{1'b0}};
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assign mul_prod_r = {2*width{1'b0}};
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assign mul_stall = 0;
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assign mul_stall = 0;
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`endif // OR1200_MULT_IMPLEMENTED
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`endif // OR1200_MULT_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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`ifdef OR1200_MAC_IMPLEMENTED
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// Signal to indicate when we should check for new MAC op
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reg ex_freeze_r;
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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ex_freeze_r <= 1'b1;
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else
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ex_freeze_r <= ex_freeze;
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//
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//
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// Propagation of l.mac opcode, only register it for one cycle
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// Propagation of l.mac opcode, only register it for one cycle
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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| Line 361... |
Line 374... |
if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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mac_stall_r <= 1'b0;
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mac_stall_r <= 1'b0;
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else
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else
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mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) &
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mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) &
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(id_macrc_op | mac_stall_r);
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(id_macrc_op | mac_stall_r);
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`else // OR1200_MAC_IMPLEMENTED
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`else // OR1200_MAC_IMPLEMENTED
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assign mac_stall_r = 1'b0;
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assign mac_stall_r = 1'b0;
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assign mac_r = {2*width{1'b0}};
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assign mac_r = {2*width{1'b0}};
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assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
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assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
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assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
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assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
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