OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Diff between revs 10 and 141

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 10 Rev 141
Line 42... Line 42...
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_mult_mac.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Bugs fixed. 
 
//
 
// Revision 1.5  2006/04/09 01:32:29  lampret
 
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
 
//
// Revision 1.4  2004/06/08 18:17:36  lampret
// Revision 1.4  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
// Non-functional changes. Coding style fixes.
//
//
// Revision 1.3  2003/04/24 00:16:07  lampret
// Revision 1.3  2003/04/24 00:16:07  lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
// No functional changes. Added defines to disable implementation of multiplier/MAC
Line 308... Line 315...
`endif
`endif
        else if (mac_op_r3 == `OR1200_MACOP_MAC)
        else if (mac_op_r3 == `OR1200_MACOP_MAC)
                mac_r <= #1 mac_r + mul_prod_r;
                mac_r <= #1 mac_r + mul_prod_r;
        else if (mac_op_r3 == `OR1200_MACOP_MSB)
        else if (mac_op_r3 == `OR1200_MACOP_MSB)
                mac_r <= #1 mac_r - mul_prod_r;
                mac_r <= #1 mac_r - mul_prod_r;
        else if (macrc_op & !ex_freeze)
        else if (macrc_op && !ex_freeze)
                mac_r <= #1 64'h0000_0000_0000_0000;
                mac_r <= #1 64'h0000_0000_0000_0000;
 
 
//
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
// in EX stage (e.g. inside multiplier)
Line 320... Line 327...
//
//
always @(posedge rst or posedge clk)
always @(posedge rst or posedge clk)
        if (rst)
        if (rst)
                mac_stall_r <= #1 1'b0;
                mac_stall_r <= #1 1'b0;
        else
        else
                mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op
                mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & (id_macrc_op | mac_stall_r)
`ifdef OR1200_IMPL_DIV
`ifdef OR1200_IMPL_DIV
                                | (|div_cntr)
                                | (|div_cntr)
`endif
`endif
                                ;
                                ;
`else // OR1200_MAC_IMPLEMENTED
`else // OR1200_MAC_IMPLEMENTED

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.