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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Top level multiplier and MAC ////
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//// OR1200's Top level multiplier, divider and MAC ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Multiplier is 32x32 however multiply instructions only ////
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//// Multiplier is 32x32 however multiply instructions only ////
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//// use lower 32 bits of the result. MAC is 32x32=64+64. ////
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//// use lower 32 bits of the result. MAC is 32x32=64+64. ////
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//// ////
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//// ////
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// $Log: or1200_mult_mac.v,v $
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// $Log: or1200_mult_mac.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Bugs fixed.
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// Bugs fixed.
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//
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//
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// Revision 1.5 2006/04/09 01:32:29 lampret
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// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts.
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//
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// Revision 1.4 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.3 2003/04/24 00:16:07 lampret
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// No functional changes. Added defines to disable implementation of multiplier/MAC
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//
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// Revision 1.2 2002/09/08 05:52:16 lampret
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// Added optional l.div/l.divu insns. By default they are disabled.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.3 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.2 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:38 igorm
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// no message
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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wire spr_maclo_we;
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wire spr_maclo_we;
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wire spr_machi_we;
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wire spr_machi_we;
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wire alu_op_div_divu;
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wire alu_op_div_divu;
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wire alu_op_div;
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wire alu_op_div;
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reg div_free;
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reg div_free;
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`ifdef OR1200_IMPL_DIV
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`ifdef OR1200_DIV_IMPLEMENTED
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wire [width-1:0] div_tmp;
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wire [width-1:0] div_tmp;
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reg [5:0] div_cntr;
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reg [5:0] div_cntr;
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`endif
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`endif
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//
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//
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assign spr_maclo_we = 1'b0;
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assign spr_maclo_we = 1'b0;
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assign spr_machi_we = 1'b0;
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assign spr_machi_we = 1'b0;
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assign spr_dat_o = 32'h0000_0000;
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assign spr_dat_o = 32'h0000_0000;
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`endif
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`endif
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`ifdef OR1200_LOWPWR_MULT
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`ifdef OR1200_LOWPWR_MULT
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assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
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assign x = (alu_op_div & a[31]) ? ~a + 1'b1 :
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assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
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alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ?
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a : 32'h0000_0000;
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assign y = (alu_op_div & b[31]) ? ~b + 1'b1 :
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alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ?
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b : 32'h0000_0000;
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`else
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`else
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assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;
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assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;
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assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;
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assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;
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`endif
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`endif
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`ifdef OR1200_IMPL_DIV
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`ifdef OR1200_DIV_IMPLEMENTED
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assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
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assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
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assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
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assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
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assign div_tmp = mul_prod_r[63:32] - y;
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assign div_tmp = mul_prod_r[63:32] - y;
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`else
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`else
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assign alu_op_div = 1'b0;
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assign alu_op_div = 1'b0;
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// Select result of current ALU operation to be forwarded
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// Select result of current ALU operation to be forwarded
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// to next instruction and to WB stage
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// to next instruction and to WB stage
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//
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//
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always @(alu_op or mul_prod_r or mac_r or a or b)
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always @(alu_op or mul_prod_r or mac_r or a or b)
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casex(alu_op) // synopsys parallel_case
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casex(alu_op) // synopsys parallel_case
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`ifdef OR1200_IMPL_DIV
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`ifdef OR1200_DIV_IMPLEMENTED
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`OR1200_ALUOP_DIV:
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`OR1200_ALUOP_DIV: begin
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result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
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result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
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end
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`OR1200_ALUOP_DIVU,
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`OR1200_ALUOP_DIVU,
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`endif
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`endif
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`OR1200_ALUOP_MUL: begin
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`OR1200_ALUOP_MUL: begin
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result = mul_prod_r[31:0];
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result = mul_prod_r[31:0];
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end
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end
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// Registered output from the multiplier and
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// Registered output from the multiplier and
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// an optional divider
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// an optional divider
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//
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//
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always @(posedge rst or posedge clk)
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always @(posedge rst or posedge clk)
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if (rst) begin
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if (rst) begin
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mul_prod_r <= #1 64'h0000_0000_0000_0000;
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mul_prod_r <= 64'h0000_0000_0000_0000;
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div_free <= #1 1'b1;
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div_free <= 1'b1;
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`ifdef OR1200_IMPL_DIV
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`ifdef OR1200_DIV_IMPLEMENTED
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div_cntr <= #1 6'b00_0000;
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div_cntr <= 6'b00_0000;
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`endif
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`endif
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end
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end
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`ifdef OR1200_IMPL_DIV
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`ifdef OR1200_DIV_IMPLEMENTED
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else if (|div_cntr) begin
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else if (|div_cntr) begin
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if (div_tmp[31])
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if (div_tmp[31])
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mul_prod_r <= #1 {mul_prod_r[62:0], 1'b0};
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mul_prod_r <= {mul_prod_r[62:0], 1'b0};
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else
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else
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mul_prod_r <= #1 {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
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mul_prod_r <= {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
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div_cntr <= #1 div_cntr - 1'b1;
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div_cntr <= div_cntr - 1'b1;
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end
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end
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else if (alu_op_div_divu && div_free) begin
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else if (alu_op_div_divu && div_free) begin
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mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};
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mul_prod_r <= {31'b0, x[31:0], 1'b0};
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div_cntr <= #1 6'b10_0000;
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div_cntr <= 6'b10_0000;
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div_free <= #1 1'b0;
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div_free <= 1'b0;
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end
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end
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`endif // OR1200_IMPL_DIV
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`endif // OR1200_DIV_IMPLEMENTED
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else if (div_free | !ex_freeze) begin
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else if (div_free | !ex_freeze) begin
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mul_prod_r <= #1 mul_prod[63:0];
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mul_prod_r <= mul_prod[63:0];
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div_free <= #1 1'b1;
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div_free <= 1'b1;
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end
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end
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`else // OR1200_MULT_IMPLEMENTED
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`else // OR1200_MULT_IMPLEMENTED
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assign result = {width{1'b0}};
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assign result = {width{1'b0}};
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assign mul_prod = {2*width{1'b0}};
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assign mul_prod = {2*width{1'b0}};
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//
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//
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// Propagation of l.mac opcode
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// Propagation of l.mac opcode
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
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mac_op_r1 <= `OR1200_MACOP_WIDTH'b0;
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else
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else
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mac_op_r1 <= #1 mac_op;
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mac_op_r1 <= mac_op;
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//
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//
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// Propagation of l.mac opcode
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// Propagation of l.mac opcode
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
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mac_op_r2 <= `OR1200_MACOP_WIDTH'b0;
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else
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else
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mac_op_r2 <= #1 mac_op_r1;
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mac_op_r2 <= mac_op_r1;
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//
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//
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// Propagation of l.mac opcode
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// Propagation of l.mac opcode
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
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mac_op_r3 <= `OR1200_MACOP_WIDTH'b0;
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else
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else
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mac_op_r3 <= #1 mac_op_r2;
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mac_op_r3 <= mac_op_r2;
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//
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//
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// Implementation of MAC
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// Implementation of MAC
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//
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//
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always @(posedge rst or posedge clk)
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always @(posedge rst or posedge clk)
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if (rst)
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if (rst)
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mac_r <= #1 64'h0000_0000_0000_0000;
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mac_r <= 64'h0000_0000_0000_0000;
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`ifdef OR1200_MAC_SPR_WE
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`ifdef OR1200_MAC_SPR_WE
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else if (spr_maclo_we)
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else if (spr_maclo_we)
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mac_r[31:0] <= #1 spr_dat_i;
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mac_r[31:0] <= spr_dat_i;
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else if (spr_machi_we)
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else if (spr_machi_we)
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mac_r[63:32] <= #1 spr_dat_i;
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mac_r[63:32] <= spr_dat_i;
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`endif
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`endif
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else if (mac_op_r3 == `OR1200_MACOP_MAC)
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else if (mac_op_r3 == `OR1200_MACOP_MAC)
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mac_r <= #1 mac_r + mul_prod_r;
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mac_r <= mac_r + mul_prod_r;
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else if (mac_op_r3 == `OR1200_MACOP_MSB)
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else if (mac_op_r3 == `OR1200_MACOP_MSB)
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mac_r <= #1 mac_r - mul_prod_r;
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mac_r <= mac_r - mul_prod_r;
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else if (macrc_op && !ex_freeze)
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else if (macrc_op && !ex_freeze)
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mac_r <= #1 64'h0000_0000_0000_0000;
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mac_r <= 64'h0000_0000_0000_0000;
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//
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//
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// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
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// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
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// in EX stage (e.g. inside multiplier)
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// in EX stage (e.g. inside multiplier)
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// This stall signal is also used by the divider.
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// This stall signal is also used by the divider.
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//
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//
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always @(posedge rst or posedge clk)
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always @(posedge rst or posedge clk)
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if (rst)
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if (rst)
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mac_stall_r <= #1 1'b0;
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mac_stall_r <= 1'b0;
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else
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else
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mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & (id_macrc_op | mac_stall_r)
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mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & (id_macrc_op | mac_stall_r)
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`ifdef OR1200_IMPL_DIV
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`ifdef OR1200_DIV_IMPLEMENTED
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| (|div_cntr)
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| (|div_cntr)
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`endif
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`endif
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;
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;
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`else // OR1200_MAC_IMPLEMENTED
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`else // OR1200_MAC_IMPLEMENTED
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assign mac_stall_r = 1'b0;
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assign mac_stall_r = 1'b0;
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