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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_operandmuxes.v] - Diff between revs 186 and 258
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| Rev 186 |
Rev 258 |
| Line 94... |
Line 94... |
//
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//
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// Operand A register
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// Operand A register
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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operand_a <= #1 32'd0;
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operand_a <= 32'd0;
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saved_a <= #1 1'b0;
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saved_a <= 1'b0;
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end else if (!ex_freeze && id_freeze && !saved_a) begin
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end else if (!ex_freeze && id_freeze && !saved_a) begin
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operand_a <= #1 muxed_a;
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operand_a <= muxed_a;
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saved_a <= #1 1'b1;
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saved_a <= 1'b1;
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end else if (!ex_freeze && !saved_a) begin
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end else if (!ex_freeze && !saved_a) begin
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operand_a <= #1 muxed_a;
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operand_a <= muxed_a;
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end else if (!ex_freeze && !id_freeze)
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end else if (!ex_freeze && !id_freeze)
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saved_a <= #1 1'b0;
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saved_a <= 1'b0;
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end
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end
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//
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//
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// Operand B register
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// Operand B register
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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operand_b <= #1 32'd0;
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operand_b <= 32'd0;
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saved_b <= #1 1'b0;
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saved_b <= 1'b0;
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end else if (!ex_freeze && id_freeze && !saved_b) begin
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end else if (!ex_freeze && id_freeze && !saved_b) begin
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operand_b <= #1 muxed_b;
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operand_b <= muxed_b;
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saved_b <= #1 1'b1;
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saved_b <= 1'b1;
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end else if (!ex_freeze && !saved_b) begin
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end else if (!ex_freeze && !saved_b) begin
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operand_b <= #1 muxed_b;
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operand_b <= muxed_b;
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end else if (!ex_freeze && !id_freeze)
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end else if (!ex_freeze && !id_freeze)
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saved_b <= #1 1'b0;
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saved_b <= 1'b0;
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end
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end
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//
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//
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// Forwarding logic for operand A register
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// Forwarding logic for operand A register
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//
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//
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