OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_operandmuxes.v] - Diff between revs 186 and 258

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 186 Rev 258
Line 94... Line 94...
//
//
// Operand A register
// Operand A register
//
//
always @(posedge clk or posedge rst) begin
always @(posedge clk or posedge rst) begin
        if (rst) begin
        if (rst) begin
                operand_a <= #1 32'd0;
                operand_a <=  32'd0;
                saved_a <= #1 1'b0;
                saved_a <=  1'b0;
        end else if (!ex_freeze && id_freeze && !saved_a) begin
        end else if (!ex_freeze && id_freeze && !saved_a) begin
                operand_a <= #1 muxed_a;
                operand_a <=  muxed_a;
                saved_a <= #1 1'b1;
                saved_a <=  1'b1;
        end else if (!ex_freeze && !saved_a) begin
        end else if (!ex_freeze && !saved_a) begin
                operand_a <= #1 muxed_a;
                operand_a <=  muxed_a;
        end else if (!ex_freeze && !id_freeze)
        end else if (!ex_freeze && !id_freeze)
                saved_a <= #1 1'b0;
                saved_a <=  1'b0;
end
end
 
 
//
//
// Operand B register
// Operand B register
//
//
always @(posedge clk or posedge rst) begin
always @(posedge clk or posedge rst) begin
        if (rst) begin
        if (rst) begin
                operand_b <= #1 32'd0;
                operand_b <=  32'd0;
                saved_b <= #1 1'b0;
                saved_b <=  1'b0;
        end else if (!ex_freeze && id_freeze && !saved_b) begin
        end else if (!ex_freeze && id_freeze && !saved_b) begin
                operand_b <= #1 muxed_b;
                operand_b <=  muxed_b;
                saved_b <= #1 1'b1;
                saved_b <=  1'b1;
        end else if (!ex_freeze && !saved_b) begin
        end else if (!ex_freeze && !saved_b) begin
                operand_b <= #1 muxed_b;
                operand_b <=  muxed_b;
        end else if (!ex_freeze && !id_freeze)
        end else if (!ex_freeze && !id_freeze)
                saved_b <= #1 1'b0;
                saved_b <=  1'b0;
end
end
 
 
//
//
// Forwarding logic for operand A register
// Forwarding logic for operand A register
//
//

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.