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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_operandmuxes.v] - Diff between revs 358 and 364
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Rev 364 |
Line 126... |
Line 126... |
//
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//
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// Forwarding logic for operand A register
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// Forwarding logic for operand A register
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//
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//
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always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
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always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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casex (sel_a) // synopsys parallel_case infer_mux
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casez (sel_a) // synopsys parallel_case infer_mux
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`else
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`else
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casex (sel_a) // synopsys parallel_case
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casez (sel_a) // synopsys parallel_case
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`endif
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`endif
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`OR1200_SEL_EX_FORW:
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`OR1200_SEL_EX_FORW:
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muxed_a = ex_forw;
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muxed_a = ex_forw;
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`OR1200_SEL_WB_FORW:
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`OR1200_SEL_WB_FORW:
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muxed_a = wb_forw;
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muxed_a = wb_forw;
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Line 144... |
Line 144... |
//
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//
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// Forwarding logic for operand B register
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// Forwarding logic for operand B register
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//
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//
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always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
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always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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casex (sel_b) // synopsys parallel_case infer_mux
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casez (sel_b) // synopsys parallel_case infer_mux
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`else
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`else
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casex (sel_b) // synopsys parallel_case
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casez (sel_b) // synopsys parallel_case
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`endif
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`endif
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`OR1200_SEL_IMM:
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`OR1200_SEL_IMM:
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muxed_b = simm;
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muxed_b = simm;
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`OR1200_SEL_EX_FORW:
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`OR1200_SEL_EX_FORW:
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muxed_b = ex_forw;
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muxed_b = ex_forw;
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