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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_operandmuxes.v] - Diff between revs 358 and 364

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Rev 358 Rev 364
Line 126... Line 126...
//
//
// Forwarding logic for operand A register
// Forwarding logic for operand A register
//
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        casex (sel_a)   // synopsys parallel_case infer_mux
        casez (sel_a)   // synopsys parallel_case infer_mux
`else
`else
        casex (sel_a)   // synopsys parallel_case
        casez (sel_a)   // synopsys parallel_case
`endif
`endif
                `OR1200_SEL_EX_FORW:
                `OR1200_SEL_EX_FORW:
                        muxed_a = ex_forw;
                        muxed_a = ex_forw;
                `OR1200_SEL_WB_FORW:
                `OR1200_SEL_WB_FORW:
                        muxed_a = wb_forw;
                        muxed_a = wb_forw;
Line 144... Line 144...
//
//
// Forwarding logic for operand B register
// Forwarding logic for operand B register
//
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
        casex (sel_b)   // synopsys parallel_case infer_mux
        casez (sel_b)   // synopsys parallel_case infer_mux
`else
`else
        casex (sel_b)   // synopsys parallel_case
        casez (sel_b)   // synopsys parallel_case
`endif
`endif
                `OR1200_SEL_IMM:
                `OR1200_SEL_IMM:
                        muxed_b = simm;
                        muxed_b = simm;
                `OR1200_SEL_EX_FORW:
                `OR1200_SEL_EX_FORW:
                        muxed_b = ex_forw;
                        muxed_b = ex_forw;

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