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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_operandmuxes.v] - Diff between revs 10 and 141

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Rev 10 Rev 141
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////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_operandmuxes.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Bugs fixed. 
 
//
 
// Revision 1.2  2002/03/29 15:16:56  lampret
 
// Some of the warnings fixed.
 
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
//
// Revision 1.9  2001/11/12 01:45:40  lampret
// Revision 1.9  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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        // Clock and reset
        // Clock and reset
        clk, rst,
        clk, rst,
 
 
        // Internal i/f
        // Internal i/f
        id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
        id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
        simm, sel_a, sel_b, operand_a, operand_b, muxed_b
        simm, sel_a, sel_b, operand_a, operand_b, muxed_a, muxed_b
);
);
 
 
parameter width = `OR1200_OPERAND_WIDTH;
parameter width = `OR1200_OPERAND_WIDTH;
 
 
//
//
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input   [width-1:0]              simm;
input   [width-1:0]              simm;
input   [`OR1200_SEL_WIDTH-1:0]  sel_a;
input   [`OR1200_SEL_WIDTH-1:0]  sel_a;
input   [`OR1200_SEL_WIDTH-1:0]  sel_b;
input   [`OR1200_SEL_WIDTH-1:0]  sel_b;
output  [width-1:0]              operand_a;
output  [width-1:0]              operand_a;
output  [width-1:0]              operand_b;
output  [width-1:0]              operand_b;
 
output  [width-1:0]              muxed_a;
output  [width-1:0]              muxed_b;
output  [width-1:0]              muxed_b;
 
 
//
//
// Internal wires and regs
// Internal wires and regs
//
//

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