| Line 41... |
Line 41... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_operandmuxes.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Bugs fixed.
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//
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// Revision 1.2 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.9 2001/11/12 01:45:40 lampret
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// Revision 1.9 2001/11/12 01:45:40 lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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| Line 76... |
Line 83... |
// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Internal i/f
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// Internal i/f
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id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
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id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
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simm, sel_a, sel_b, operand_a, operand_b, muxed_b
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simm, sel_a, sel_b, operand_a, operand_b, muxed_a, muxed_b
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);
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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//
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//
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| Line 97... |
Line 104... |
input [width-1:0] simm;
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input [width-1:0] simm;
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input [`OR1200_SEL_WIDTH-1:0] sel_a;
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input [`OR1200_SEL_WIDTH-1:0] sel_a;
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input [`OR1200_SEL_WIDTH-1:0] sel_b;
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input [`OR1200_SEL_WIDTH-1:0] sel_b;
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output [width-1:0] operand_a;
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output [width-1:0] operand_a;
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output [width-1:0] operand_b;
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output [width-1:0] operand_b;
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output [width-1:0] muxed_a;
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output [width-1:0] muxed_b;
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output [width-1:0] muxed_b;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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