OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Diff between revs 141 and 258

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 141 Rev 258
Line 1... Line 1...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  OR1200's Programmable Interrupt Controller                  ////
////  OR1200's Programmable Interrupt Controller                  ////
////                                                              ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  PIC according to OR1K architectural specification.          ////
////  PIC according to OR1K architectural specification.          ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
Line 39... Line 39...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
 
//
 
// $Log: or1200_pic.v,v $
// $Log: or1200_pic.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// No update 
 
//
 
// Revision 1.4  2004/06/08 18:17:36  lampret
 
// Non-functional changes. Coding style fixes.
 
//
 
// Revision 1.3  2002/03/29 15:16:56  lampret
 
// Some of the warnings fixed.
 
//
 
// Revision 1.2  2002/01/18 07:56:00  lampret
 
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
 
//
 
// Revision 1.1  2002/01/03 08:16:15  lampret
 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
 
//
 
// Revision 1.8  2001/10/21 17:57:16  lampret
 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
 
//
 
// Revision 1.7  2001/10/14 13:12:10  lampret
 
// MP3 version.
 
//
 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
 
// no message
 
//
 
// Revision 1.2  2001/08/09 13:39:33  lampret
 
// Major clean-up.
 
//
 
// Revision 1.1  2001/07/20 00:46:21  lampret
 
// Development version of RTL. Libraries are missing.
 
//
 
//
//
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
Line 149... Line 118...
`ifdef OR1200_PIC_PICMR
`ifdef OR1200_PIC_PICMR
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
        else if (picmr_sel && spr_write) begin
        else if (picmr_sel && spr_write) begin
                picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
                picmr <=  spr_dat_i[`OR1200_PIC_INTS-1:2];
        end
        end
`else
`else
assign picmr = (`OR1200_PIC_INTS)'b1;
assign picmr = (`OR1200_PIC_INTS)'b1;
`endif
`endif
 
 
Line 163... Line 132...
`ifdef OR1200_PIC_PICSR
`ifdef OR1200_PIC_PICSR
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                picsr <= {`OR1200_PIC_INTS{1'b0}};
                picsr <= {`OR1200_PIC_INTS{1'b0}};
        else if (picsr_sel && spr_write) begin
        else if (picsr_sel && spr_write) begin
                picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
                picsr <=  spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
        end else
        end else
                picsr <= #1 picsr | um_ints;
                picsr <=  picsr | um_ints;
`else
`else
assign picsr = pic_int;
assign picsr = pic_int;
`endif
`endif
 
 
//
//
Line 177... Line 146...
//
//
always @(spr_addr or picmr or picsr)
always @(spr_addr or picmr or picsr)
        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys parallel_case
        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys parallel_case
`ifdef OR1200_PIC_READREGS
`ifdef OR1200_PIC_READREGS
                `OR1200_PIC_OFS_PICMR: begin
                `OR1200_PIC_OFS_PICMR: begin
                                        spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
                   spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b11};
`ifdef OR1200_PIC_UNUSED_ZERO
`ifdef OR1200_PIC_UNUSED_ZERO
                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
`endif
                                end
                                end
`endif
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.