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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Diff between revs 258 and 358

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Rev 258 Rev 358
Line 114... Line 114...
 
 
//
//
// Write to PICMR
// Write to PICMR
//
//
`ifdef OR1200_PIC_PICMR
`ifdef OR1200_PIC_PICMR
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
        else if (picmr_sel && spr_write) begin
        else if (picmr_sel && spr_write) begin
                picmr <=  spr_dat_i[`OR1200_PIC_INTS-1:2];
                picmr <=  spr_dat_i[`OR1200_PIC_INTS-1:2];
        end
        end
`else
`else
Line 128... Line 128...
 
 
//
//
// Write to PICSR, both CPU and external ints
// Write to PICSR, both CPU and external ints
//
//
`ifdef OR1200_PIC_PICSR
`ifdef OR1200_PIC_PICSR
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                picsr <= {`OR1200_PIC_INTS{1'b0}};
                picsr <= {`OR1200_PIC_INTS{1'b0}};
        else if (picsr_sel && spr_write) begin
        else if (picsr_sel && spr_write) begin
                picsr <=  spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
                picsr <=  spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;
        end else
        end else
                picsr <=  picsr | um_ints;
                picsr <=  picsr | um_ints;

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