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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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//
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//
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// Write to PMR and also PMR[DME]/PMR[SME] reset when
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// Write to PMR and also PMR[DME]/PMR[SME] reset when
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// pic_wakeup is asserted
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// pic_wakeup is asserted
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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{dcge, sme, dme, sdf} <= 7'b0;
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{dcge, sme, dme, sdf} <= 7'b0;
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else if (pmr_sel && spr_write) begin
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else if (pmr_sel && spr_write) begin
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sdf <= spr_dat_i[`OR1200_PM_PMR_SDF];
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sdf <= spr_dat_i[`OR1200_PM_PMR_SDF];
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dme <= spr_dat_i[`OR1200_PM_PMR_DME];
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dme <= spr_dat_i[`OR1200_PM_PMR_DME];
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sme <= spr_dat_i[`OR1200_PM_PMR_SME];
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sme <= spr_dat_i[`OR1200_PM_PMR_SME];
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