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Line 319... |
//
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//
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// QMEM control FSM
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// QMEM control FSM
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//
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//
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always @(posedge rst or posedge clk)
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always @(posedge rst or posedge clk)
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if (rst) begin
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if (rst) begin
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state <= #1 `OR1200_QMEMFSM_IDLE;
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state <= `OR1200_QMEMFSM_IDLE;
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qmem_dack <= #1 1'b0;
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qmem_dack <= 1'b0;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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else case (state) // synopsys parallel_case
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else case (state) // synopsys parallel_case
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`OR1200_QMEMFSM_IDLE: begin
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`OR1200_QMEMFSM_IDLE: begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_STORE;
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state <= `OR1200_QMEMFSM_STORE;
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qmem_dack <= #1 1'b1;
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qmem_dack <= 1'b1;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_LOAD;
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state <= `OR1200_QMEMFSM_LOAD;
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qmem_dack <= #1 1'b1;
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qmem_dack <= 1'b1;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_FETCH;
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state <= `OR1200_QMEMFSM_FETCH;
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qmem_iack <= #1 1'b1;
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qmem_iack <= 1'b1;
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qmem_dack <= #1 1'b0;
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qmem_dack <= 1'b0;
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end
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end
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end
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end
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`OR1200_QMEMFSM_STORE: begin
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`OR1200_QMEMFSM_STORE: begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_STORE;
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state <= `OR1200_QMEMFSM_STORE;
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qmem_dack <= #1 1'b1;
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qmem_dack <= 1'b1;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_LOAD;
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state <= `OR1200_QMEMFSM_LOAD;
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qmem_dack <= #1 1'b1;
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qmem_dack <= 1'b1;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_FETCH;
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state <= `OR1200_QMEMFSM_FETCH;
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qmem_iack <= #1 1'b1;
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qmem_iack <= 1'b1;
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qmem_dack <= #1 1'b0;
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qmem_dack <= 1'b0;
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end
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end
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else begin
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else begin
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state <= #1 `OR1200_QMEMFSM_IDLE;
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state <= `OR1200_QMEMFSM_IDLE;
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qmem_dack <= #1 1'b0;
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qmem_dack <= 1'b0;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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end
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end
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`OR1200_QMEMFSM_LOAD: begin
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`OR1200_QMEMFSM_LOAD: begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_STORE;
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state <= `OR1200_QMEMFSM_STORE;
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qmem_dack <= #1 1'b1;
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qmem_dack <= 1'b1;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_LOAD;
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state <= `OR1200_QMEMFSM_LOAD;
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qmem_dack <= #1 1'b1;
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qmem_dack <= 1'b1;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_FETCH;
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state <= `OR1200_QMEMFSM_FETCH;
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qmem_iack <= #1 1'b1;
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qmem_iack <= 1'b1;
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qmem_dack <= #1 1'b0;
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qmem_dack <= 1'b0;
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end
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end
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else begin
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else begin
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state <= #1 `OR1200_QMEMFSM_IDLE;
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state <= `OR1200_QMEMFSM_IDLE;
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qmem_dack <= #1 1'b0;
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qmem_dack <= 1'b0;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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end
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end
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`OR1200_QMEMFSM_FETCH: begin
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`OR1200_QMEMFSM_FETCH: begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_STORE;
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state <= `OR1200_QMEMFSM_STORE;
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qmem_dack <= #1 1'b1;
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qmem_dack <= 1'b1;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_LOAD;
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state <= `OR1200_QMEMFSM_LOAD;
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qmem_dack <= #1 1'b1;
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qmem_dack <= 1'b1;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
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state <= #1 `OR1200_QMEMFSM_FETCH;
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state <= `OR1200_QMEMFSM_FETCH;
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qmem_iack <= #1 1'b1;
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qmem_iack <= 1'b1;
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qmem_dack <= #1 1'b0;
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qmem_dack <= 1'b0;
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end
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end
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else begin
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else begin
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state <= #1 `OR1200_QMEMFSM_IDLE;
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state <= `OR1200_QMEMFSM_IDLE;
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qmem_dack <= #1 1'b0;
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qmem_dack <= 1'b0;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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end
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end
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default: begin
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default: begin
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state <= #1 `OR1200_QMEMFSM_IDLE;
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state <= `OR1200_QMEMFSM_IDLE;
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qmem_dack <= #1 1'b0;
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qmem_dack <= 1'b0;
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qmem_iack <= #1 1'b0;
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qmem_iack <= 1'b0;
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end
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end
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endcase
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endcase
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//
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//
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// Instantiation of embedded memory
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// Instantiation of embedded memory
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