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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_qmem_top.v] - Diff between revs 141 and 258

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//
//
// QMEM control FSM
// QMEM control FSM
//
//
always @(posedge rst or posedge clk)
always @(posedge rst or posedge clk)
        if (rst) begin
        if (rst) begin
                state <= #1 `OR1200_QMEMFSM_IDLE;
                state <=  `OR1200_QMEMFSM_IDLE;
                qmem_dack <= #1 1'b0;
                qmem_dack <=  1'b0;
                qmem_iack <= #1 1'b0;
                qmem_iack <=  1'b0;
        end
        end
        else case (state)       // synopsys parallel_case
        else case (state)       // synopsys parallel_case
                `OR1200_QMEMFSM_IDLE: begin
                `OR1200_QMEMFSM_IDLE: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                state <=  `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_dack <=  1'b1;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                state <=  `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_dack <=  1'b1;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                state <=  `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_iack <=  1'b1;
                                qmem_dack <= #1 1'b0;
                                qmem_dack <=  1'b0;
                        end
                        end
                end
                end
                `OR1200_QMEMFSM_STORE: begin
                `OR1200_QMEMFSM_STORE: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                state <=  `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_dack <=  1'b1;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                state <=  `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_dack <=  1'b1;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                state <=  `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_iack <=  1'b1;
                                qmem_dack <= #1 1'b0;
                                qmem_dack <=  1'b0;
                        end
                        end
                        else begin
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                state <=  `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_dack <=  1'b0;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                end
                end
                `OR1200_QMEMFSM_LOAD: begin
                `OR1200_QMEMFSM_LOAD: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                state <=  `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_dack <=  1'b1;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                state <=  `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_dack <=  1'b1;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                state <=  `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_iack <=  1'b1;
                                qmem_dack <= #1 1'b0;
                                qmem_dack <=  1'b0;
                        end
                        end
                        else begin
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                state <=  `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_dack <=  1'b0;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                end
                end
                `OR1200_QMEMFSM_FETCH: begin
                `OR1200_QMEMFSM_FETCH: begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                        if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_STORE;
                                state <=  `OR1200_QMEMFSM_STORE;
                                qmem_dack <= #1 1'b1;
                                qmem_dack <=  1'b1;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                        else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_LOAD;
                                state <=  `OR1200_QMEMFSM_LOAD;
                                qmem_dack <= #1 1'b1;
                                qmem_dack <=  1'b1;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                        else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
                                state <= #1 `OR1200_QMEMFSM_FETCH;
                                state <=  `OR1200_QMEMFSM_FETCH;
                                qmem_iack <= #1 1'b1;
                                qmem_iack <=  1'b1;
                                qmem_dack <= #1 1'b0;
                                qmem_dack <=  1'b0;
                        end
                        end
                        else begin
                        else begin
                                state <= #1 `OR1200_QMEMFSM_IDLE;
                                state <=  `OR1200_QMEMFSM_IDLE;
                                qmem_dack <= #1 1'b0;
                                qmem_dack <=  1'b0;
                                qmem_iack <= #1 1'b0;
                                qmem_iack <=  1'b0;
                        end
                        end
                end
                end
                default: begin
                default: begin
                        state <= #1 `OR1200_QMEMFSM_IDLE;
                        state <=  `OR1200_QMEMFSM_IDLE;
                        qmem_dack <= #1 1'b0;
                        qmem_dack <=  1'b0;
                        qmem_iack <= #1 1'b0;
                        qmem_iack <=  1'b0;
                end
                end
        endcase
        endcase
 
 
//
//
// Instantiation of embedded memory
// Instantiation of embedded memory

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