OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_reg2mem.v] - Diff between revs 141 and 364

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 141 Rev 364
Line 102... Line 102...
 
 
//
//
// Mux to memdata[31:24]
// Mux to memdata[31:24]
//
//
always @(lsu_op or addr or regdata) begin
always @(lsu_op or addr or regdata) begin
        casex({lsu_op, addr[1:0]})       // synopsys parallel_case
        casez({lsu_op, addr[1:0]})       // synopsys parallel_case
                {`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
                {`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
                {`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
                {`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
                default : memdata_hh = regdata[31:24];
                default : memdata_hh = regdata[31:24];
        endcase
        endcase
end
end
 
 
//
//
// Mux to memdata[23:16]
// Mux to memdata[23:16]
//
//
always @(lsu_op or addr or regdata) begin
always @(lsu_op or addr or regdata) begin
        casex({lsu_op, addr[1:0]})       // synopsys parallel_case
        casez({lsu_op, addr[1:0]})       // synopsys parallel_case
                {`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
                {`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
                default : memdata_hl = regdata[7:0];
                default : memdata_hl = regdata[7:0];
        endcase
        endcase
end
end
 
 
//
//
// Mux to memdata[15:8]
// Mux to memdata[15:8]
//
//
always @(lsu_op or addr or regdata) begin
always @(lsu_op or addr or regdata) begin
        casex({lsu_op, addr[1:0]})       // synopsys parallel_case
        casez({lsu_op, addr[1:0]})       // synopsys parallel_case
                {`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
                {`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
                default : memdata_lh = regdata[15:8];
                default : memdata_lh = regdata[15:8];
        endcase
        endcase
end
end
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.