| Line 102... |
Line 102... |
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//
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//
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// Mux to memdata[31:24]
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// Mux to memdata[31:24]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys parallel_case
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casez({lsu_op, addr[1:0]}) // synopsys parallel_case
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{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
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{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
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{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
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{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
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default : memdata_hh = regdata[31:24];
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default : memdata_hh = regdata[31:24];
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endcase
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endcase
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end
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end
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//
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//
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// Mux to memdata[23:16]
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// Mux to memdata[23:16]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys parallel_case
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casez({lsu_op, addr[1:0]}) // synopsys parallel_case
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{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
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{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
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default : memdata_hl = regdata[7:0];
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default : memdata_hl = regdata[7:0];
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endcase
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endcase
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end
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end
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//
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//
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// Mux to memdata[15:8]
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// Mux to memdata[15:8]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys parallel_case
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casez({lsu_op, addr[1:0]}) // synopsys parallel_case
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{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
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{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
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default : memdata_lh = regdata[15:8];
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default : memdata_lh = regdata[15:8];
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endcase
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endcase
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end
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end
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