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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Diff between revs 358 and 643

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Rev 358 Rev 643
Line 195... Line 195...
        if (rst == `OR1200_RST_VALUE)
        if (rst == `OR1200_RST_VALUE)
                rf_we_allow <=  1'b1;
                rf_we_allow <=  1'b1;
        else if (~wb_freeze)
        else if (~wb_freeze)
                rf_we_allow <=  ~flushpipe;
                rf_we_allow <=  ~flushpipe;
 
 
//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
 
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
//assign cy_we_o = cy_we_i && rf_we;
 
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
 
 
 
 
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
 
 
//
//
// CS RF A asserted when instruction reads operand A and ID stage
// CS RF A asserted when instruction reads operand A and ID stage
// is not stalled
// is not stalled
//
//
//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;      // probably works with fixed binutils
 
// assign rf_ena = 1'b1;                        // does not work with single-stepping
 
//assign rf_ena = ~id_freeze | spr_valid;       // works with broken binutils 
 
 
 
//
//
// CS RF B asserted when instruction reads operand B and ID stage
// CS RF B asserted when instruction reads operand B and ID stage
// is not stalled
// is not stalled
//
//
//assign rf_enb = rdb & ~id_freeze | spr_valid;
 
assign rf_enb = rdb & ~id_freeze;
assign rf_enb = rdb & ~id_freeze;
// assign rf_enb = 1'b1;
 
//assign rf_enb = ~id_freeze | spr_valid;       // works with broken binutils 
 
 
 
`ifdef OR1200_RFRAM_TWOPORT
`ifdef OR1200_RFRAM_TWOPORT
 
 
//
//
// Instantiation of register file two-port RAM A
// Instantiation of register file two-port RAM A

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