| Line 61... |
Line 61... |
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// Read i/f
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// Read i/f
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id_freeze, addra, addrb, dataa, datab, rda, rdb,
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id_freeze, addra, addrb, dataa, datab, rda, rdb,
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// Debug
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// Debug
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, du_read
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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| Line 108... |
Line 108... |
input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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input [31:0] spr_addr;
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input [31:0] spr_addr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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output [31:0] spr_dat_o;
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output [31:0] spr_dat_o;
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input du_read;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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wire [dw-1:0] from_rfa;
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wire [dw-1:0] from_rfa;
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| Line 123... |
Line 124... |
wire spr_valid;
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wire spr_valid;
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wire rf_ena;
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wire rf_ena;
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wire rf_enb;
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wire rf_enb;
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reg rf_we_allow;
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reg rf_we_allow;
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// Logic to restore output on RFA after debug unit has read out via SPR if.
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// Problem was that the incorrect output would be on RFA after debug unit
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// had read out - this is bad if that output is relied upon by execute
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// stage for next instruction. We simply save the last address for rf A and
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// and re-read it whenever the SPR select goes low, so we must remember
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// the last address and generate a signal for falling edge of SPR cs.
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// -- Julius
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// Detect falling edge of SPR select
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reg spr_du_cs;
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wire spr_cs_fe;
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// Track RF A's address each time it's enabled
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reg [aw-1:0] addra_last;
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always @(posedge clk)
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if (rf_ena & !(spr_cs_fe | (du_read & spr_cs)))
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addra_last <= addra;
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always @(posedge clk)
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spr_du_cs <= spr_cs & du_read;
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assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);
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//
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//
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// SPR access is valid when spr_cs is asserted and
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// SPR access is valid when spr_cs is asserted and
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// SPR address matches GPR addresses
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// SPR address matches GPR addresses
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//
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//
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assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
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assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
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| Line 147... |
Line 173... |
assign datab = from_rfb;
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assign datab = from_rfb;
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//
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//
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// RF A read address is either from SPRS or normal from CPU control
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// RF A read address is either from SPRS or normal from CPU control
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//
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//
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assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
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assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] :
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spr_cs_fe ? addra_last : addra;
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//
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//
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// RF write address is either from SPRS or normal from CPU control
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// RF write address is either from SPRS or normal from CPU control
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//
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//
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assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
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assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
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| Line 164... |
Line 191... |
//
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//
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// RF write enable is either from SPRS or normal from CPU control
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// RF write enable is either from SPRS or normal from CPU control
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//
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//
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always @(posedge rst or posedge clk)
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always @(posedge rst or posedge clk)
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if (rst)
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if (rst)
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rf_we_allow <= #1 1'b1;
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rf_we_allow <= 1'b1;
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else if (~wb_freeze)
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else if (~wb_freeze)
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rf_we_allow <= #1 ~flushpipe;
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rf_we_allow <= ~flushpipe;
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//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
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//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
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assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
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assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
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//assign cy_we_o = cy_we_i && rf_we;
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//assign cy_we_o = cy_we_i && rf_we;
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assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
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assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
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//
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//
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// CS RF A asserted when instruction reads operand A and ID stage
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// CS RF A asserted when instruction reads operand A and ID stage
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// is not stalled
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// is not stalled
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//
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//
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//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
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//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
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assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write); // probably works with fixed binutils
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assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe; // probably works with fixed binutils
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// assign rf_ena = 1'b1; // does not work with single-stepping
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// assign rf_ena = 1'b1; // does not work with single-stepping
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//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils
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//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils
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//
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//
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// CS RF B asserted when instruction reads operand B and ID stage
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// CS RF B asserted when instruction reads operand B and ID stage
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