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Line 41... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_rf.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Bugs fixed, coding style changed.
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//
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// Revision 1.3 2003/04/07 01:21:56 lampret
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// RFRAM type always need to be defined.
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//
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// Revision 1.2 2002/06/08 16:19:09 lampret
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// Revision 1.2 2002/06/08 16:19:09 lampret
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// Added generic flip-flop based memory macro instantiation.
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// Added generic flip-flop based memory macro instantiation.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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Line 97... |
module or1200_rf(
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module or1200_rf(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Write i/f
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// Write i/f
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supv, wb_freeze, addrw, dataw, we, flushpipe,
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cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
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// Read i/f
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// Read i/f
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id_freeze, addra, addrb, dataa, datab, rda, rdb,
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id_freeze, addra, addrb, dataa, datab, rda, rdb,
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// Debug
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// Debug
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Line 122... |
input rst;
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input rst;
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//
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//
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// Write i/f
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// Write i/f
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//
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//
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input cy_we_i;
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output cy_we_o;
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input supv;
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input supv;
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input wb_freeze;
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input wb_freeze;
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input [aw-1:0] addrw;
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input [aw-1:0] addrw;
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input [dw-1:0] dataw;
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input [dw-1:0] dataw;
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input we;
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input we;
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Line 156... |
//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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wire [dw-1:0] from_rfa;
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wire [dw-1:0] from_rfa;
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wire [dw-1:0] from_rfb;
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wire [dw-1:0] from_rfb;
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reg [dw:0] dataa_saved;
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reg [dw:0] datab_saved;
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wire [aw-1:0] rf_addra;
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wire [aw-1:0] rf_addra;
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wire [aw-1:0] rf_addrw;
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wire [aw-1:0] rf_addrw;
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wire [dw-1:0] rf_dataw;
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wire [dw-1:0] rf_dataw;
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wire rf_we;
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wire rf_we;
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wire spr_valid;
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wire spr_valid;
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Line 179... |
assign spr_dat_o = from_rfa;
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assign spr_dat_o = from_rfa;
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//
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//
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// Operand A comes from RF or from saved A register
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// Operand A comes from RF or from saved A register
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//
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//
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assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
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assign dataa = from_rfa;
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//
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//
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// Operand B comes from RF or from saved B register
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// Operand B comes from RF or from saved B register
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//
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//
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assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
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assign datab = from_rfb;
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//
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//
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// RF A read address is either from SPRS or normal from CPU control
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// RF A read address is either from SPRS or normal from CPU control
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//
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//
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assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
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assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
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Line 210... |
if (rst)
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if (rst)
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rf_we_allow <= #1 1'b1;
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rf_we_allow <= #1 1'b1;
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else if (~wb_freeze)
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else if (~wb_freeze)
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rf_we_allow <= #1 ~flushpipe;
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rf_we_allow <= #1 ~flushpipe;
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assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
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//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
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assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
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//assign cy_we_o = cy_we_i && rf_we;
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assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
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//
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//
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// CS RF A asserted when instruction reads operand A and ID stage
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// CS RF A asserted when instruction reads operand A and ID stage
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// is not stalled
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// is not stalled
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//
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//
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assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
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//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
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assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write); // probably works with fixed binutils
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// assign rf_ena = 1'b1; // does not work with single-stepping
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// assign rf_ena = 1'b1; // does not work with single-stepping
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//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils
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//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils
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//
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//
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// CS RF B asserted when instruction reads operand B and ID stage
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// CS RF B asserted when instruction reads operand B and ID stage
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// is not stalled
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// is not stalled
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//
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//
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assign rf_enb = rdb & ~id_freeze | spr_valid;
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//assign rf_enb = rdb & ~id_freeze | spr_valid;
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assign rf_enb = rdb & ~id_freeze;
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// assign rf_enb = 1'b1;
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// assign rf_enb = 1'b1;
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//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils
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//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils
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//
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// Stores operand from RF_A into temp reg when pipeline is frozen
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//
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always @(posedge clk or posedge rst)
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if (rst) begin
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dataa_saved <= #1 33'b0;
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end
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else if (id_freeze & !dataa_saved[32]) begin
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dataa_saved <= #1 {1'b1, from_rfa};
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end
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else if (!id_freeze)
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dataa_saved <= #1 33'b0;
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//
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// Stores operand from RF_B into temp reg when pipeline is frozen
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//
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always @(posedge clk or posedge rst)
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if (rst) begin
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datab_saved <= #1 33'b0;
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end
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else if (id_freeze & !datab_saved[32]) begin
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datab_saved <= #1 {1'b1, from_rfb};
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end
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else if (!id_freeze)
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datab_saved <= #1 33'b0;
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`ifdef OR1200_RFRAM_TWOPORT
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`ifdef OR1200_RFRAM_TWOPORT
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//
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//
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// Instantiation of register file two-port RAM A
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// Instantiation of register file two-port RAM A
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//
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//
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Line 292... |
`ifdef OR1200_RFRAM_DUALPORT
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`ifdef OR1200_RFRAM_DUALPORT
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//
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//
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// Instantiation of register file two-port RAM A
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// Instantiation of register file two-port RAM A
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//
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//
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or1200_dpram_32x32 rf_a(
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or1200_dpram #
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(
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.aw(5),
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.dw(32)
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)
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rf_a
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(
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// Port A
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// Port A
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.clk_a(clk),
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.clk_a(clk),
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.rst_a(rst),
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.ce_a(rf_ena),
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.ce_a(rf_ena),
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.oe_a(1'b1),
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.addr_a(rf_addra),
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.addr_a(rf_addra),
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.do_a(from_rfa),
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.do_a(from_rfa),
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// Port B
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// Port B
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.clk_b(clk),
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.clk_b(clk),
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.rst_b(rst),
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.ce_b(rf_we),
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.ce_b(rf_we),
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.we_b(rf_we),
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.we_b(rf_we),
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.addr_b(rf_addrw),
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.addr_b(rf_addrw),
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.di_b(rf_dataw)
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.di_b(rf_dataw)
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);
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);
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//
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//
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// Instantiation of register file two-port RAM B
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// Instantiation of register file two-port RAM B
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//
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//
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or1200_dpram_32x32 rf_b(
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or1200_dpram #
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(
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.aw(5),
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.dw(32)
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)
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rf_b
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(
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// Port A
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// Port A
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.clk_a(clk),
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.clk_a(clk),
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.rst_a(rst),
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.ce_a(rf_enb),
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.ce_a(rf_enb),
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.oe_a(1'b1),
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.addr_a(addrb),
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.addr_a(addrb),
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.do_a(from_rfb),
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.do_a(from_rfb),
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// Port B
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// Port B
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.clk_b(clk),
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.clk_b(clk),
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.rst_b(rst),
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.ce_b(rf_we),
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.ce_b(rf_we),
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.we_b(rf_we),
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.we_b(rf_we),
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.addr_b(rf_addrw),
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.addr_b(rf_addrw),
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.di_b(rf_dataw)
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.di_b(rf_dataw)
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);
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);
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