URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rf.v] - Diff between revs 258 and 358

Rev 258	Rev 358
Line 189...	Line 189...
`assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;`	`assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;`

`//`	`//`
`// RF write enable is either from SPRS or normal from CPU control`	`// RF write enable is either from SPRS or normal from CPU control`
`//`	`//`
`always @(posedge rst or posedge clk)`	always @(`OR1200_RST_EVENT rst or posedge clk)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`rf_we_allow <= 1'b1;`	`rf_we_allow <= 1'b1;`
`else if (~wb_freeze)`	`else if (~wb_freeze)`
`rf_we_allow <= ~flushpipe;`	`rf_we_allow <= ~flushpipe;`

`//assign rf_we = ((spr_valid & spr_write) \| (we & ~wb_freeze)) & rf_we_allow & (supv \| (\|rf_addrw));`	`//assign rf_we = ((spr_valid & spr_write) \| (we & ~wb_freeze)) & rf_we_allow & (supv \| (\|rf_addrw));`