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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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// $Log: not supported by cvs2svn $
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//
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// $Log: or1200_rfram_generic.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Defines added, coding style changed.
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//
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// Revision 1.3 2004/06/08 18:16:32 lampret
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// GPR0 hardwired to zero.
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//
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// Revision 1.2 2002/09/03 22:28:21 lampret
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// Revision 1.2 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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//
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// Revision 1.1 2002/06/08 16:23:30 lampret
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// Revision 1.1 2002/06/08 16:23:30 lampret
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// Generic flip-flop based memory macro for register file.
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// Generic flip-flop based memory macro for register file.
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Line 116... |
//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [aw-1:0] intaddr_a;
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reg [aw-1:0] intaddr_a;
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reg [aw-1:0] intaddr_b;
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reg [aw-1:0] intaddr_b;
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`ifdef OR1200_RFRAM_16REG
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reg [16*dw-1:0] mem;
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`else
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reg [32*dw-1:0] mem;
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reg [32*dw-1:0] mem;
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`endif
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reg [dw-1:0] do_a;
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reg [dw-1:0] do_a;
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reg [dw-1:0] do_b;
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reg [dw-1:0] do_b;
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// Function to access GPRs (for use by Verilator). No need to hide this one
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// from the simulator, since it has an input (as required by IEEE 1364-2001).
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function [31:0] get_gpr;
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// verilator public
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input [aw-1:0] gpr_no;
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get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
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mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
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mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
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mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
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mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
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mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
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mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
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mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
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mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
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mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
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mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
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mem[gpr_no*32 + 9], mem[gpr_no*32 + 8],
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mem[gpr_no*32 + 7], mem[gpr_no*32 + 6],
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mem[gpr_no*32 + 5], mem[gpr_no*32 + 4],
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mem[gpr_no*32 + 3], mem[gpr_no*32 + 2],
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mem[gpr_no*32 + 1], mem[gpr_no*32 + 0] };
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endfunction // get_gpr
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//
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//
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// Write port
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// Write port
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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mem <= #1 {512'h0, 512'h0};
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mem <= #1 {512'h0, 512'h0};
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end
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end
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else if (ce_w & we_w)
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else if (ce_w & we_w)
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case (addr_w) // synopsys parallel_case
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case (addr_w) // synopsys parallel_case
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5'd00: mem[32*0+31:32*0] <= #1 32'h0000_0000;
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5'd01: mem[32*1+31:32*1] <= #1 di_w;
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5'd01: mem[32*1+31:32*1] <= #1 di_w;
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5'd02: mem[32*2+31:32*2] <= #1 di_w;
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5'd02: mem[32*2+31:32*2] <= #1 di_w;
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5'd03: mem[32*3+31:32*3] <= #1 di_w;
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5'd03: mem[32*3+31:32*3] <= #1 di_w;
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5'd04: mem[32*4+31:32*4] <= #1 di_w;
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5'd04: mem[32*4+31:32*4] <= #1 di_w;
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5'd05: mem[32*5+31:32*5] <= #1 di_w;
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5'd05: mem[32*5+31:32*5] <= #1 di_w;
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Line 173... |
5'd11: mem[32*11+31:32*11] <= #1 di_w;
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5'd11: mem[32*11+31:32*11] <= #1 di_w;
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5'd12: mem[32*12+31:32*12] <= #1 di_w;
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5'd12: mem[32*12+31:32*12] <= #1 di_w;
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5'd13: mem[32*13+31:32*13] <= #1 di_w;
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5'd13: mem[32*13+31:32*13] <= #1 di_w;
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5'd14: mem[32*14+31:32*14] <= #1 di_w;
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5'd14: mem[32*14+31:32*14] <= #1 di_w;
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5'd15: mem[32*15+31:32*15] <= #1 di_w;
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5'd15: mem[32*15+31:32*15] <= #1 di_w;
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`ifdef OR1200_RFRAM_16REG
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`else
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5'd16: mem[32*16+31:32*16] <= #1 di_w;
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5'd16: mem[32*16+31:32*16] <= #1 di_w;
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5'd17: mem[32*17+31:32*17] <= #1 di_w;
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5'd17: mem[32*17+31:32*17] <= #1 di_w;
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5'd18: mem[32*18+31:32*18] <= #1 di_w;
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5'd18: mem[32*18+31:32*18] <= #1 di_w;
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5'd19: mem[32*19+31:32*19] <= #1 di_w;
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5'd19: mem[32*19+31:32*19] <= #1 di_w;
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5'd20: mem[32*20+31:32*20] <= #1 di_w;
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5'd20: mem[32*20+31:32*20] <= #1 di_w;
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Line 190... |
5'd26: mem[32*26+31:32*26] <= #1 di_w;
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5'd26: mem[32*26+31:32*26] <= #1 di_w;
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5'd27: mem[32*27+31:32*27] <= #1 di_w;
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5'd27: mem[32*27+31:32*27] <= #1 di_w;
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5'd28: mem[32*28+31:32*28] <= #1 di_w;
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5'd28: mem[32*28+31:32*28] <= #1 di_w;
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5'd29: mem[32*29+31:32*29] <= #1 di_w;
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5'd29: mem[32*29+31:32*29] <= #1 di_w;
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5'd30: mem[32*30+31:32*30] <= #1 di_w;
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5'd30: mem[32*30+31:32*30] <= #1 di_w;
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default: mem[32*31+31:32*31] <= #1 di_w;
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5'd31: mem[32*31+31:32*31] <= #1 di_w;
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`endif
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default: mem[32*0+31:32*0] <= #1 32'h0000_0000;
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endcase
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endcase
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//
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//
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// Read port A
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// Read port A
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//
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//
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Line 207... |
else if (ce_a)
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else if (ce_a)
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intaddr_a <= #1 addr_a;
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intaddr_a <= #1 addr_a;
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always @(mem or intaddr_a)
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always @(mem or intaddr_a)
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case (intaddr_a) // synopsys parallel_case
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case (intaddr_a) // synopsys parallel_case
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5'd00: do_a = 32'h0000_0000;
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5'd01: do_a = mem[32*1+31:32*1];
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5'd01: do_a = mem[32*1+31:32*1];
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5'd02: do_a = mem[32*2+31:32*2];
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5'd02: do_a = mem[32*2+31:32*2];
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5'd03: do_a = mem[32*3+31:32*3];
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5'd03: do_a = mem[32*3+31:32*3];
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5'd04: do_a = mem[32*4+31:32*4];
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5'd04: do_a = mem[32*4+31:32*4];
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5'd05: do_a = mem[32*5+31:32*5];
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5'd05: do_a = mem[32*5+31:32*5];
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Line 222... |
5'd11: do_a = mem[32*11+31:32*11];
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5'd11: do_a = mem[32*11+31:32*11];
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5'd12: do_a = mem[32*12+31:32*12];
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5'd12: do_a = mem[32*12+31:32*12];
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5'd13: do_a = mem[32*13+31:32*13];
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5'd13: do_a = mem[32*13+31:32*13];
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5'd14: do_a = mem[32*14+31:32*14];
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5'd14: do_a = mem[32*14+31:32*14];
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5'd15: do_a = mem[32*15+31:32*15];
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5'd15: do_a = mem[32*15+31:32*15];
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`ifdef OR1200_RFRAM_16REG
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`else
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5'd16: do_a = mem[32*16+31:32*16];
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5'd16: do_a = mem[32*16+31:32*16];
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5'd17: do_a = mem[32*17+31:32*17];
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5'd17: do_a = mem[32*17+31:32*17];
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5'd18: do_a = mem[32*18+31:32*18];
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5'd18: do_a = mem[32*18+31:32*18];
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5'd19: do_a = mem[32*19+31:32*19];
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5'd19: do_a = mem[32*19+31:32*19];
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5'd20: do_a = mem[32*20+31:32*20];
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5'd20: do_a = mem[32*20+31:32*20];
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Line 239... |
5'd26: do_a = mem[32*26+31:32*26];
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5'd26: do_a = mem[32*26+31:32*26];
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5'd27: do_a = mem[32*27+31:32*27];
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5'd27: do_a = mem[32*27+31:32*27];
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5'd28: do_a = mem[32*28+31:32*28];
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5'd28: do_a = mem[32*28+31:32*28];
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5'd29: do_a = mem[32*29+31:32*29];
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5'd29: do_a = mem[32*29+31:32*29];
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5'd30: do_a = mem[32*30+31:32*30];
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5'd30: do_a = mem[32*30+31:32*30];
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default: do_a = mem[32*31+31:32*31];
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5'd31: do_a = mem[32*31+31:32*31];
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`endif
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default: do_a = 32'h0000_0000;
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endcase
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endcase
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//
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//
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// Read port B
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// Read port B
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//
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//
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| Line 213... |
Line 256... |
else if (ce_b)
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else if (ce_b)
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intaddr_b <= #1 addr_b;
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intaddr_b <= #1 addr_b;
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always @(mem or intaddr_b)
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always @(mem or intaddr_b)
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case (intaddr_b) // synopsys parallel_case
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case (intaddr_b) // synopsys parallel_case
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5'd00: do_b = 32'h0000_0000;
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5'd01: do_b = mem[32*1+31:32*1];
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5'd01: do_b = mem[32*1+31:32*1];
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5'd02: do_b = mem[32*2+31:32*2];
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5'd02: do_b = mem[32*2+31:32*2];
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5'd03: do_b = mem[32*3+31:32*3];
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5'd03: do_b = mem[32*3+31:32*3];
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5'd04: do_b = mem[32*4+31:32*4];
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5'd04: do_b = mem[32*4+31:32*4];
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5'd05: do_b = mem[32*5+31:32*5];
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5'd05: do_b = mem[32*5+31:32*5];
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Line 271... |
5'd11: do_b = mem[32*11+31:32*11];
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5'd11: do_b = mem[32*11+31:32*11];
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5'd12: do_b = mem[32*12+31:32*12];
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5'd12: do_b = mem[32*12+31:32*12];
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5'd13: do_b = mem[32*13+31:32*13];
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5'd13: do_b = mem[32*13+31:32*13];
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5'd14: do_b = mem[32*14+31:32*14];
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5'd14: do_b = mem[32*14+31:32*14];
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5'd15: do_b = mem[32*15+31:32*15];
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5'd15: do_b = mem[32*15+31:32*15];
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`ifdef OR1200_RFRAM_16REG
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`else
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5'd16: do_b = mem[32*16+31:32*16];
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5'd16: do_b = mem[32*16+31:32*16];
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5'd17: do_b = mem[32*17+31:32*17];
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5'd17: do_b = mem[32*17+31:32*17];
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5'd18: do_b = mem[32*18+31:32*18];
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5'd18: do_b = mem[32*18+31:32*18];
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5'd19: do_b = mem[32*19+31:32*19];
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5'd19: do_b = mem[32*19+31:32*19];
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5'd20: do_b = mem[32*20+31:32*20];
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5'd20: do_b = mem[32*20+31:32*20];
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| Line 244... |
Line 288... |
5'd26: do_b = mem[32*26+31:32*26];
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5'd26: do_b = mem[32*26+31:32*26];
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5'd27: do_b = mem[32*27+31:32*27];
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5'd27: do_b = mem[32*27+31:32*27];
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5'd28: do_b = mem[32*28+31:32*28];
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5'd28: do_b = mem[32*28+31:32*28];
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5'd29: do_b = mem[32*29+31:32*29];
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5'd29: do_b = mem[32*29+31:32*29];
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5'd30: do_b = mem[32*30+31:32*30];
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5'd30: do_b = mem[32*30+31:32*30];
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default: do_b = mem[32*31+31:32*31];
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5'd31: do_b = mem[32*31+31:32*31];
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`endif
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default: do_b = 32'h0000_0000;
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endcase
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endcase
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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