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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Store Buffer ////
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//// OR1200's Store Buffer ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Implements store buffer. ////
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//// Implements store buffer. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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//
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// $Log: or1200_sb.v,v $
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// $Log: or1200_sb.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Bugs fixed.
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// Bugs fixed.
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//
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// Revision 1.2 2002/08/22 02:18:55 lampret
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// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
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//
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// Revision 1.1 2002/08/18 19:53:08 lampret
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// Added store buffer.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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sb_en_reg <= 1'b0;
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sb_en_reg <= 1'b0;
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else if (sb_en & ~dcsb_cyc_i)
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else if (sb_en & ~dcsb_cyc_i)
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sb_en_reg <= #1 1'b1; // enable SB when there is no dcsb transfer in progress
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sb_en_reg <= 1'b1; // enable SB when there is no dcsb transfer in progress
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else if (~sb_en & (~fifo_empty | (fifo_empty & outstanding_store)))
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else if (~sb_en & (~fifo_empty | (fifo_empty & outstanding_store)))
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sb_en_reg <= #1 1'b0; // disable SB when there is no pending transfers from SB
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sb_en_reg <= 1'b0; // disable SB when there is no pending transfers from SB
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//
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//
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// Store buffer FIFO instantiation
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// Store buffer FIFO instantiation
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//
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//
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or1200_sb_fifo or1200_sb_fifo (
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or1200_sb_fifo or1200_sb_fifo (
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//
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//
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// fifo_rd
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// fifo_rd
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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outstanding_store <= #1 1'b0;
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outstanding_store <= 1'b0;
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else if (sbbiu_ack_i)
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else if (sbbiu_ack_i)
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outstanding_store <= #1 1'b0;
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outstanding_store <= 1'b0;
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else if (sel_sb | fifo_wr)
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else if (sel_sb | fifo_wr)
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outstanding_store <= #1 1'b1;
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outstanding_store <= 1'b1;
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//
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//
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// fifo_wr_ack
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// fifo_wr_ack
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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fifo_wr_ack <= #1 1'b0;
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fifo_wr_ack <= 1'b0;
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else if (fifo_wr)
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else if (fifo_wr)
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fifo_wr_ack <= #1 1'b1;
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fifo_wr_ack <= 1'b1;
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else
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else
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fifo_wr_ack <= #1 1'b0;
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fifo_wr_ack <= 1'b0;
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`else // !OR1200_SB_IMPLEMENTED
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`else // !OR1200_SB_IMPLEMENTED
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assign sbbiu_dat_o = dcsb_dat_i;
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assign sbbiu_dat_o = dcsb_dat_i;
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assign sbbiu_adr_o = dcsb_adr_i;
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assign sbbiu_adr_o = dcsb_adr_i;
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