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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_sb.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Bugs fixed.
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//
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// Revision 1.2 2002/08/22 02:18:55 lampret
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// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
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//
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// Revision 1.1 2002/08/18 19:53:08 lampret
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// Revision 1.1 2002/08/18 19:53:08 lampret
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// Added store buffer.
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// Added store buffer.
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//
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//
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//
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//
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Line 63... |
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module or1200_sb(
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module or1200_sb(
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// RISC clock, reset
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// RISC clock, reset
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clk, rst,
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clk, rst,
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// Internal RISC bus (SB)
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sb_en,
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// Internal RISC bus (DC<->SB)
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// Internal RISC bus (DC<->SB)
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dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i,
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dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i,
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dcsb_dat_o, dcsb_ack_o, dcsb_err_o,
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dcsb_dat_o, dcsb_ack_o, dcsb_err_o,
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// BIU bus
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// BIU bus
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Line 85... |
//
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//
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input clk; // RISC clock
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input clk; // RISC clock
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input rst; // RISC reset
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input rst; // RISC reset
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//
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//
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// Internal RISC bus (SB)
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//
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input sb_en; // SB enable
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//
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// Internal RISC bus (DC<->SB)
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// Internal RISC bus (DC<->SB)
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//
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//
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input [dw-1:0] dcsb_dat_i; // input data bus
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input [dw-1:0] dcsb_dat_i; // input data bus
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input [aw-1:0] dcsb_adr_i; // address bus
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input [aw-1:0] dcsb_adr_i; // address bus
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input dcsb_cyc_i; // WB cycle
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input dcsb_cyc_i; // WB cycle
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Line 129... |
wire fifo_wr;
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wire fifo_wr;
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wire fifo_rd;
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wire fifo_rd;
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wire fifo_full;
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wire fifo_full;
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wire fifo_empty;
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wire fifo_empty;
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wire sel_sb;
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wire sel_sb;
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reg sb_en_reg;
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reg outstanding_store;
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reg outstanding_store;
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reg fifo_wr_ack;
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reg fifo_wr_ack;
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//
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//
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// FIFO data in/out
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// FIFO data in/out
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Line 151... |
assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error
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assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error
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assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i;
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assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i;
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assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i;
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assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i;
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assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i;
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assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i;
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assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i;
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assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i;
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assign sel_sb = ~fifo_empty | (fifo_empty & outstanding_store); // | fifo_wr;
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assign sel_sb = sb_en_reg & (~fifo_empty | (fifo_empty & outstanding_store));
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//
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// SB enable
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//
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always @(posedge clk or posedge rst)
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if (rst)
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sb_en_reg <= 1'b0;
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else if (sb_en & ~dcsb_cyc_i)
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sb_en_reg <= #1 1'b1; // enable SB when there is no dcsb transfer in progress
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else if (~sb_en & (~fifo_empty | (fifo_empty & outstanding_store)))
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sb_en_reg <= #1 1'b0; // disable SB when there is no pending transfers from SB
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//
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//
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// Store buffer FIFO instantiation
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// Store buffer FIFO instantiation
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//
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//
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or1200_sb_fifo or1200_sb_fifo (
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or1200_sb_fifo or1200_sb_fifo (
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