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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sb.v] - Diff between revs 141 and 258

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  OR1200's Store Buffer                                       ////
////  OR1200's Store Buffer                                       ////
////                                                              ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////  http://opencores.org/project,or1k                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Implements store buffer.                                    ////
////  Implements store buffer.                                    ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
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//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
 
//
//
// $Log: or1200_sb.v,v $
// $Log: or1200_sb.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Minor update: 
// Bugs fixed. 
// Bugs fixed. 
//
 
// Revision 1.2  2002/08/22 02:18:55  lampret
 
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
 
//
 
// Revision 1.1  2002/08/18 19:53:08  lampret
 
// Added store buffer.
 
//
 
//
 
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"
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//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                sb_en_reg <= 1'b0;
                sb_en_reg <= 1'b0;
        else if (sb_en & ~dcsb_cyc_i)
        else if (sb_en & ~dcsb_cyc_i)
                sb_en_reg <= #1 1'b1; // enable SB when there is no dcsb transfer in progress
                sb_en_reg <=  1'b1; // enable SB when there is no dcsb transfer in progress
        else if (~sb_en & (~fifo_empty | (fifo_empty & outstanding_store)))
        else if (~sb_en & (~fifo_empty | (fifo_empty & outstanding_store)))
                sb_en_reg <= #1 1'b0; // disable SB when there is no pending transfers from SB
                sb_en_reg <=  1'b0; // disable SB when there is no pending transfers from SB
 
 
//
//
// Store buffer FIFO instantiation
// Store buffer FIFO instantiation
//
//
or1200_sb_fifo or1200_sb_fifo (
or1200_sb_fifo or1200_sb_fifo (
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//
//
// fifo_rd
// fifo_rd
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                outstanding_store <= #1 1'b0;
                outstanding_store <=  1'b0;
        else if (sbbiu_ack_i)
        else if (sbbiu_ack_i)
                outstanding_store <= #1 1'b0;
                outstanding_store <=  1'b0;
        else if (sel_sb | fifo_wr)
        else if (sel_sb | fifo_wr)
                outstanding_store <= #1 1'b1;
                outstanding_store <=  1'b1;
 
 
//
//
// fifo_wr_ack
// fifo_wr_ack
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                fifo_wr_ack <= #1 1'b0;
                fifo_wr_ack <=  1'b0;
        else if (fifo_wr)
        else if (fifo_wr)
                fifo_wr_ack <= #1 1'b1;
                fifo_wr_ack <=  1'b1;
        else
        else
                fifo_wr_ack <= #1 1'b0;
                fifo_wr_ack <=  1'b0;
 
 
`else   // !OR1200_SB_IMPLEMENTED
`else   // !OR1200_SB_IMPLEMENTED
 
 
assign sbbiu_dat_o = dcsb_dat_i;
assign sbbiu_dat_o = dcsb_dat_i;
assign sbbiu_adr_o = dcsb_adr_i;
assign sbbiu_adr_o = dcsb_adr_i;

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