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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sb.v] - Diff between revs 258 and 358

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Rev 258 Rev 358
Line 147... Line 147...
assign sel_sb = sb_en_reg & (~fifo_empty | (fifo_empty & outstanding_store));
assign sel_sb = sb_en_reg & (~fifo_empty | (fifo_empty & outstanding_store));
 
 
//
//
// SB enable
// SB enable
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                sb_en_reg <= 1'b0;
                sb_en_reg <= 1'b0;
        else if (sb_en & ~dcsb_cyc_i)
        else if (sb_en & ~dcsb_cyc_i)
                sb_en_reg <=  1'b1; // enable SB when there is no dcsb transfer in progress
                sb_en_reg <=  1'b1; // enable SB when there is no dcsb transfer in progress
        else if (~sb_en & (~fifo_empty | (fifo_empty & outstanding_store)))
        else if (~sb_en & (~fifo_empty | (fifo_empty & outstanding_store)))
                sb_en_reg <=  1'b0; // disable SB when there is no pending transfers from SB
                sb_en_reg <=  1'b0; // disable SB when there is no pending transfers from SB
Line 172... Line 172...
);
);
 
 
//
//
// fifo_rd
// fifo_rd
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                outstanding_store <=  1'b0;
                outstanding_store <=  1'b0;
        else if (sbbiu_ack_i)
        else if (sbbiu_ack_i)
                outstanding_store <=  1'b0;
                outstanding_store <=  1'b0;
        else if (sel_sb | fifo_wr)
        else if (sel_sb | fifo_wr)
                outstanding_store <=  1'b1;
                outstanding_store <=  1'b1;
 
 
//
//
// fifo_wr_ack
// fifo_wr_ack
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                fifo_wr_ack <=  1'b0;
                fifo_wr_ack <=  1'b0;
        else if (fifo_wr)
        else if (fifo_wr)
                fifo_wr_ack <=  1'b1;
                fifo_wr_ack <=  1'b1;
        else
        else
                fifo_wr_ack <=  1'b0;
                fifo_wr_ack <=  1'b0;

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