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| Rev 141 |
Rev 258 |
| Line 94... |
Line 94... |
reg empty_o;
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reg empty_o;
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reg full_o;
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reg full_o;
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always @(posedge clk_i or posedge rst_i)
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always @(posedge clk_i or posedge rst_i)
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if (rst_i) begin
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if (rst_i) begin
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full_o <= #1 1'b0;
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full_o <= 1'b0;
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empty_o <= #1 1'b1;
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empty_o <= 1'b1;
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wr_pntr <= #1 {fw{1'b0}};
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wr_pntr <= {fw{1'b0}};
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rd_pntr <= #1 {fw{1'b0}};
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rd_pntr <= {fw{1'b0}};
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cntr <= #1 {fw+2{1'b0}};
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cntr <= {fw+2{1'b0}};
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dat_o <= #1 {dw{1'b0}};
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dat_o <= {dw{1'b0}};
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end
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end
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else if (wr_i && rd_i) begin // FIFO Read and Write
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else if (wr_i && rd_i) begin // FIFO Read and Write
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mem[wr_pntr] <= #1 dat_i;
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mem[wr_pntr] <= dat_i;
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if (wr_pntr >= fl-1)
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if (wr_pntr >= fl-1)
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wr_pntr <= #1 {fw{1'b0}};
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wr_pntr <= {fw{1'b0}};
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else
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else
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wr_pntr <= #1 wr_pntr + 1'b1;
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wr_pntr <= wr_pntr + 1'b1;
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if (empty_o) begin
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if (empty_o) begin
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dat_o <= #1 dat_i;
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dat_o <= dat_i;
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end
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end
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else begin
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else begin
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dat_o <= #1 mem[rd_pntr];
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dat_o <= mem[rd_pntr];
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end
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end
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if (rd_pntr >= fl-1)
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if (rd_pntr >= fl-1)
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rd_pntr <= #1 {fw{1'b0}};
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rd_pntr <= {fw{1'b0}};
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else
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else
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rd_pntr <= #1 rd_pntr + 1'b1;
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rd_pntr <= rd_pntr + 1'b1;
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end
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end
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else if (wr_i && !full_o) begin // FIFO Write
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else if (wr_i && !full_o) begin // FIFO Write
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mem[wr_pntr] <= #1 dat_i;
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mem[wr_pntr] <= dat_i;
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cntr <= #1 cntr + 1'b1;
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cntr <= cntr + 1'b1;
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empty_o <= #1 1'b0;
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empty_o <= 1'b0;
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if (cntr >= (fl-1)) begin
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if (cntr >= (fl-1)) begin
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full_o <= #1 1'b1;
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full_o <= 1'b1;
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cntr <= #1 fl;
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cntr <= fl;
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end
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end
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if (wr_pntr >= fl-1)
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if (wr_pntr >= fl-1)
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wr_pntr <= #1 {fw{1'b0}};
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wr_pntr <= {fw{1'b0}};
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else
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else
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wr_pntr <= #1 wr_pntr + 1'b1;
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wr_pntr <= wr_pntr + 1'b1;
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end
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end
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else if (rd_i && !empty_o) begin // FIFO Read
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else if (rd_i && !empty_o) begin // FIFO Read
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dat_o <= #1 mem[rd_pntr];
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dat_o <= mem[rd_pntr];
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cntr <= #1 cntr - 1'b1;
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cntr <= cntr - 1'b1;
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full_o <= #1 1'b0;
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full_o <= 1'b0;
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if (cntr <= 1) begin
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if (cntr <= 1) begin
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empty_o <= #1 1'b1;
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empty_o <= 1'b1;
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cntr <= #1 {fw+2{1'b0}};
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cntr <= {fw+2{1'b0}};
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end
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end
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if (rd_pntr >= fl-1)
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if (rd_pntr >= fl-1)
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rd_pntr <= #1 {fw{1'b0}};
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rd_pntr <= {fw{1'b0}};
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else
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else
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rd_pntr <= #1 rd_pntr + 1'b1;
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rd_pntr <= rd_pntr + 1'b1;
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end
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end
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endmodule
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endmodule
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