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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram.v] - Diff between revs 142 and 258

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Rev 142 Rev 258
Line 102... Line 102...
   //
   //
 
 
   //
   //
   // Generic RAM's registers and wires
   // Generic RAM's registers and wires
   //
   //
`ifdef OR1200_ACTEL
`ifdef OR1200_GENERIC
   reg [dw-1:0]                    mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [dw-1:0]                    mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
`else
   reg [dw-1:0]                    mem [(1<<aw)-1:0];
   reg [dw-1:0]                    mem [(1<<aw)-1:0];
`endif
`endif
   reg [aw-1:0]                    addr_reg;             // RAM address register
   reg [aw-1:0]                    addr_reg;             // RAM address register
Line 120... Line 120...
   //
   //
   // RAM read address register
   // RAM read address register
   //
   //
   always @(posedge clk)
   always @(posedge clk)
     if (ce)
     if (ce)
       addr_reg <= #1 addr;
       addr_reg <=  addr;
 
 
   //
   //
   // RAM write
   // RAM write
   //
   //
   always @(posedge clk)
   always @(posedge clk)
     if (we && ce)
     if (we && ce)
       mem[addr] <= #1 di;
       mem[addr] <=  di;
 
 
endmodule // or1200_spram
endmodule // or1200_spram
 
 
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