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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x32.v] - Diff between revs 10 and 142

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Rev 10 Rev 142
Line 61... Line 61...
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_1024x32.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Coding style changed.
 
//
 
// Revision 1.9  2005/10/19 11:37:56  jcastillo
 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
 
//
// Revision 1.8  2004/06/08 18:15:32  lampret
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
// Changed behavior of the simulation generic models
//
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
// Merged branch_qmem into main tree.
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//
//
// Block 0
// Block 0
//
//
RAMB4_S4 ramb4_s4_0(
RAMB4_S4 ramb4_s4_0(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[3:0]),
        .DI(di[3:0]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[3:0])
        .DO(doq[3:0])
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//
//
// Block 1
// Block 1
//
//
RAMB4_S4 ramb4_s4_1(
RAMB4_S4 ramb4_s4_1(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[7:4]),
        .DI(di[7:4]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[7:4])
        .DO(doq[7:4])
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//
//
// Block 2
// Block 2
//
//
RAMB4_S4 ramb4_s4_2(
RAMB4_S4 ramb4_s4_2(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[11:8]),
        .DI(di[11:8]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[11:8])
        .DO(doq[11:8])
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//
//
// Block 3
// Block 3
//
//
RAMB4_S4 ramb4_s4_3(
RAMB4_S4 ramb4_s4_3(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[15:12]),
        .DI(di[15:12]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[15:12])
        .DO(doq[15:12])
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//
//
// Block 4
// Block 4
//
//
RAMB4_S4 ramb4_s4_4(
RAMB4_S4 ramb4_s4_4(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[19:16]),
        .DI(di[19:16]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[19:16])
        .DO(doq[19:16])
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//
//
// Block 5
// Block 5
//
//
RAMB4_S4 ramb4_s4_5(
RAMB4_S4 ramb4_s4_5(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[23:20]),
        .DI(di[23:20]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[23:20])
        .DO(doq[23:20])
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//
//
// Block 6
// Block 6
//
//
RAMB4_S4 ramb4_s4_6(
RAMB4_S4 ramb4_s4_6(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[27:24]),
        .DI(di[27:24]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[27:24])
        .DO(doq[27:24])
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//
//
// Block 7
// Block 7
//
//
RAMB4_S4 ramb4_s4_7(
RAMB4_S4 ramb4_s4_7(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[31:28]),
        .DI(di[31:28]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[31:28])
        .DO(doq[31:28])
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//
//
// Block 0
// Block 0
//
//
RAMB16_S9 ramb16_s9_0(
RAMB16_S9 ramb16_s9_0(
        .CLK(clk),
        .CLK(clk),
        .SSR(rst),
        .SSR(1'b0),
        .ADDR({1'b0,addr}),
        .ADDR({1'b0,addr}),
        .DI(di[7:0]),
        .DI(di[7:0]),
        .DIP(1'b0),
        .DIP(1'b0),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
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//
//
// Block 1
// Block 1
//
//
RAMB16_S9 ramb16_s9_1(
RAMB16_S9 ramb16_s9_1(
        .CLK(clk),
        .CLK(clk),
        .SSR(rst),
        .SSR(1'b0),
        .ADDR({1'b0,addr}),
        .ADDR({1'b0,addr}),
        .DI(di[15:8]),
        .DI(di[15:8]),
        .DIP(1'b0),
        .DIP(1'b0),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
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//
//
// Block 2
// Block 2
//
//
RAMB16_S9 ramb16_s9_2(
RAMB16_S9 ramb16_s9_2(
        .CLK(clk),
        .CLK(clk),
        .SSR(rst),
        .SSR(1'b0),
        .ADDR({1'b0,addr}),
        .ADDR({1'b0,addr}),
        .DI(di[23:16]),
        .DI(di[23:16]),
        .DIP(1'b0),
        .DIP(1'b0),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
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//
//
// Block 3
// Block 3
//
//
RAMB16_S9 ramb16_s9_3(
RAMB16_S9 ramb16_s9_3(
        .CLK(clk),
        .CLK(clk),
        .SSR(rst),
        .SSR(1'b0),
        .ADDR({1'b0,addr}),
        .ADDR({1'b0,addr}),
        .DI(di[31:24]),
        .DI(di[31:24]),
        .DIP(1'b0),
        .DIP(1'b0),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),

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